UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 572

• Manufacturer Part Number: UPD78F1144AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1144AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
<R>
14.5.6 Holding DMA transfer pending by DWAITn
the CPU is stopped and delayed for the duration of 2 clocks. If this poses a problem to the operation of the set
system, a DMA transfer can be held pending by setting DWAITn to 1. The DMA transfer for a transfer trigger that
occurred while DMA transfer was held pending is executed after the pending status is canceled. However, because
only one transfer trigger can be held pending for each channel, even if multiple transfer triggers occur for one channel
during the pending status, only one DMA transfer is executed after the pending status is canceled.
width increases to 12 if a DMA transfer is started midway. In this case, the DMA transfer can be held pending by
setting DWAITn to 1.
570
When DMA transfer is started, transfer is performed while an instruction is executed. At this time, the operation of
To output a pulse with a width of 10 clocks of the operating frequency from the P00 pin, for example, the clock
After setting DWAITn to 1, it takes two clocks until a DMA transfer is held pending.
Remarks 1. n: DMA channel number (n = 0, 1)
Caution
2. 1 clock: 1/f
Figure 14-12. Example of Setting for Holding DMA Transfer Pending by DWAITn
When DMA transfer is held pending while using both DMA channels, be sure to hold the DMA
transfer pending for both channels (by setting DWAIT0 and DWAIT1 to 1). If the DMA transfer
of one channel is executed while that of the other channel is held pending, DMA transfer might
not be held pending for the latter channel.
CLK
(f
CLK
: CPU clock)
CHAPTER 14 DMA CONTROLLER
User’s Manual U17854EJ9V0UD
Starting DMA transfer
Wait for 2 clocks
Wait for 9 clocks
Main program
DWAITn = 1
DWAITn = 0
P10 = 1
P10 = 0