UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 601

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UPD78F1144AGB-GAH-AX

Manufacturer Part Number
UPD78F1144AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1144AGB-GAH-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number:
UPD78F1144AGB-GAH-AX
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Quantity:
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Part Number:
UPD78F1144AGB-GAH-AX
Manufacturer:
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Quantity:
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<R>
16.3 Register Controlling Key Interrupt
Symbol
Address: FFF27H
PM7
(1) Key return mode register (KRM)
Cautions 1. If any of the KRM0 to KRM7 bits used is set to 1, set bits 0 to 7 (PU70 to PU77) of the
Remark
(2) Port mode register 7 (PM7)
Remark
This register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals, respectively.
KRM can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
This register sets the input or output of port 7 in 1-bit units.
When using the P70/KR0, P71/KR1, P72/KR2, P73/KR3, P74/KR4/INTP8, P75/KR5/INTP9, P76/KR6/
INTP10, P77/KR7/INTP11 pins as the key interrupt function, set both PM70 to PM77 to 1. The output latches
of P70 to P77 at this time may be 0 or 1.
PM7 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
PM77
PM7n
7
0
1
2. An interrupt will be generated if the target bit of the KRM register is set while a low level is
3. The bits not used in the key interrupt mode can be used as normal ports.
n = 0 to 7
Symbol
Address: FFF37H
KRM
corresponding pull-up resistor register 7 (PU7) to 1.
being input to the key interrupt input pin. To ignore this interrupt, set the KRM register after
disabling interrupt servicing by using the interrupt mask flag. Afterward, clear the interrupt
request flag and enable interrupt servicing after waiting for the key interrupt input low-level
width (250 ns or more).
n = 0 to 7
After reset: FFH
Output mode (output buffer on)
Input mode (output buffer off)
PM76
6
KRMn
KRM7
Figure 16-2. Format of Key Return Mode Register (KRM)
0
1
7
Figure 16-3. Format of Port Mode Register 7 (PM7)
Does not detect key interrupt signal
Detects key interrupt signal
R/W
After reset: 00H
KRM6
CHAPTER 16 KEY INTERRUPT FUNCTION
PM75
6
5
User’s Manual U17854EJ9V0UD
KRM5
5
P7n pin I/O mode selection (n = 0 to 7)
PM74
4
R/W
KRM4
Key interrupt mode control
4
PM73
KRM3
3
3
KRM2
2
PM72
2
KRM1
PM71
1
KRM0
0
PM70
0
599

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