UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 603

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UPD78F1144AGB-GAH-AX

Manufacturer Part Number
UPD78F1144AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1144AGB-GAH-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1144AGB-GAH-AX
Manufacturer:
RENESAS
Quantity:
1 000
Part Number:
UPD78F1144AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
(1) Oscillation stabilization time counter status register (OSTC)
This is the register that indicates the count status of the X1 clock oscillation stabilization time counter.
The X1 clock oscillation stabilization time can be checked in the following case,
OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset is released (reset by RESET input, POC, LVI, WDT, and executing an illegal instruction), the STOP
instruction and MSTOP (bit 7 of CSC register) = 1 clear this register to 00H.
Address: FFFA2H
Symbol
• If the X1 clock starts oscillation while the internal high-speed oscillation clock or subsystem clock is being
• If the STOP mode is entered and then released while the internal high-speed oscillation clock is being used
OSTC
used as the CPU clock.
as the CPU clock with the X1 clock oscillating.
Figure 17-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Remark f
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST8 and
MOST
MOST
7
8
8
0
1
1
1
1
1
1
1
1
MOST
MOST
After reset: 00H
6
9
9
0
0
1
1
1
1
1
1
1
2. The oscillation stabilization time counter counts up to the oscillation
3. The X1 clock oscillation stabilization wait time does not include the time until
X
: X1 clock oscillation frequency
remain 1.
stabilization time set by OSTS. If the STOP mode is entered and then released
while the internal high-speed oscillation clock is being used as the CPU clock,
set the oscillation stabilization time as follows.
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
clock oscillation starts (“a” below).
MOST
MOST
10
10
5
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time
0
0
0
1
1
1
1
1
1
X1 pin voltage
waveform
set by OSTS
MOST
MOST
CHAPTER 17 STANDBY FUNCTION
11
11
4
0
0
0
0
1
1
1
1
1
R
User’s Manual U17854EJ9V0UD
MOST
MOST
STOP mode release
13
13
3
0
0
0
0
0
1
1
1
1
MOST
MOST
15
15
2
0
0
0
0
0
0
1
1
1
a
MOST
MOST
17
17
1
0
0
0
0
0
0
0
1
1
MOST
MOST
18
18
0
0
0
0
0
0
0
0
1
0
2
2
2
2
2
2
2
2
2
8
8
9
10
11
13
15
17
18
/f
/f
/f
/f
/f
/f
/f
/f
/f
Oscillation stabilization time status
X
X
X
X
X
X
X
X
X
max. 25.6
min. 25.6
min. 51.2
min. 102.4
min. 204.8
min. 819.2
min. 3.27 ms min.
min. 13.11 ms min. 6.55 ms min.
min. 26.21 ms min. 13.11 ms min.
f
X
= 10 MHz
μ
μ
μ
s max.
s min.
s min.
μ
μ
μ
s min. 51.2
s min. 102.4
s min. 409.6
12.8
12.8
25.6
1.64 ms min.
f
X
= 20 MHz
μ
μ
μ
μ
s max.
s min.
s min.
s min.
μ
μ
s min.
s min.
601

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