UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 632

• Manufacturer Part Number: UPD78F1144AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1144AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.1 Functions of Low-Voltage Detector
pin is more than or less than the detection level can be checked by reading the low-voltage detection flag (LVIF: bit 0
of LVIM).
reset occurs. For details of RESF, see CHAPTER 18 RESET FUNCTION.
630
Selects reset (LVIMD = 1).
Generates an internal reset
signal when V
releases the reset signal when
V
DD
The low-voltage detector (LVI) has the following functions.
• The LVI circuit compares the supply voltage (V
• The low-voltage detector (LVI) can be set to ON by an option byte by default. If it is set to ON to raise the power
• The supply voltage (V
• A reset or an interrupt can be selected to be generated after detection by software.
• Detection levels (V
• Operable in STOP mode.
The reset and interrupt signals are generated as follows depending on selection by software.
Remark LVISEL: Bit 2 of low-voltage detection register (LVIM)
While the low-voltage detector is operating, whether the supply voltage or the input voltage from an external input
When the low-voltage detector is used to reset, bit 0 (LVIRF) of the reset control flag register (RESF) is set to 1 if
≥ V
external input pin (EXLVI) with the detection voltage (V
or internal interrupt signal.
supply from the POC detection voltage or lower, the internal reset signal
voltage (V
when the supply voltage (V
by software.
Note
Selection of Level Detection of Supply Voltage (V
LVI
.
DD
See the timing in Figure 19-2 (2) When LVI is ON upon power application (option byte: LVIOFF = 0)
for the reset processing time until the normal operation is entered after the LVI reset is released.
LVIMD: Bit 1 of LVIM
< V
DD
) < detection voltage (V
LVI
and
(LVISEL = 0)
LVI
,16 levels) of supply voltage can be changed by software.
DD
) or the input voltage from the external input pin (EXLVI) can be selected to be detected
Selects interrupt (LVIMD = 0).
Generates an internal interrupt
signal when V
than V
V
(V
DD
DD
CHAPTER 20 LOW-VOLTAGE DETECTOR
DD
becomes V
≥ V
) < detection voltage (V
LVI
LVI
(V
).
DD
DD
< V
LVI
LVI
drops lower
User’s Manual U17854EJ9V0UD
LVI
= 2.07 V ±0.2 V). After that, the internal reset signal
or higher
) or when
DD
)
DD
) with the detection voltage (V
LVI
Selects reset (LVIMD = 1).
Generates an internal reset
signal when EXLVI < V
and releases the reset signal
when EXLVI ≥ V
EXLVI
= 2.07 V ±0.1 V).
= 1.21 V ±0.1 V), and generates an internal reset
Selection Level Detection of Input Voltage from
External Input Pin (EXLVI) (LVISEL = 1)
EXLVI
.
EXLVI
Note
LVI
is generated when the supply
) or the input voltage from an
Selects interrupt (LVIMD = 0).
Generates an internal interrupt
signal when EXLVI drops
lower than V
V
becomes V
(EXLVI ≥ V
EXLVI
) or when EXLVI
EXLVI
EXLVI
EXLVI
Note
).
or higher
(EXLVI <
is generated
Note