UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 74

• Manufacturer Part Number: UPD78F1144AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1144AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

72
FFFB0H
FFFB1H
FFFB2H
FFFB3H
FFFB4H
FFFB5H
FFFB6H
FFFB7H
FFFB8H
FFFB9H
FFFBAH
FFFBBH
FFFBCH
FFFBDH
FFFBEH
FFFC0H
FFFC2H
FFFC4H
FFFD0H
FFFD1H
FFFD4H
FFFD5H
FFFD8H
FFFD9H
FFFDCH
FFFDDH
FFFE0H
FFFE1H
FFFE2H
FFFE3H
FFFE4H
FFFE5H
FFFE6H
FFFE7H
FFFE8H
FFFE9H
FFFEAH
FFFEBH
FFFECH
FFFEDH
Address
Note
Do not directly operate this SFR, because it is to be used in the self programming library.
DMA SFR address register 0
DMA SFR address register 1
DMA RAM address register 0L
DMA RAM address register 0H
DMA RAM address register 1L
DMA RAM address register 1H
DMA byte count register 0L
DMA byte count register 0H
DMA byte count register 1L
DMA byte count register 1H
DMA mode control register 0
DMA mode control register 1
DMA operation control register 0
DMA operation control register 1
Back ground event control register
Interrupt request flag register 2L
Interrupt request flag register 2H
Interrupt mask flag register 2L
Interrupt mask flag register 2H
Priority specification flag register 02L
Priority specification flag register 02H
Priority specification flag register 12L
Priority specification flag register 12H
Interrupt request flag register 0L
Interrupt request flag register 0H
Interrupt request flag register 1L
Interrupt request flag register 1H
Interrupt mask flag register 0L
Interrupt mask flag register 0H
Interrupt mask flag register 1L
Interrupt mask flag register 1H
Priority specification flag register 00L
Priority specification flag register 00H
Priority specification flag register 01L
Priority specification flag register 01H
Priority specification flag register 10L
Priority specification flag register 10H
Special Function Register (SFR) Name
−
−
−
CHAPTER 3 CPU ARCHITECTURE
Table 3-5. SFR List (4/5)
User’s Manual U17854EJ9V0UD
DSA0
DSA1
DRA0L
DRA0H
DRA1L
DRA1H
DBC0L
DBC0H
DBC1L
DBC1H
DMC0
DMC1
DRC0
DRC1
BECTL
PFCMD
PFS
FLPMC
IF2L
IF2H
MK2L
MK2H
PR02L
PR02H
PR12L
PR12H
IF0L
IF0H
IF1L
IF1H
MK0L
MK0H
MK1L
MK1H
PR00L
PR00H
PR01L
PR01H
PR10L
PR10H
Note
Symbol
Note
Note
DRA0
DRA1
DBC0
DBC1
IF2
MK2
PR02
PR12
IF0
IF1
MK0
MK1
PR00
PR01
PR10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
−
−
−
Manipulable Bit Range
1-bit
−
−
−
−
−
−
−
−
−
−
√
√
√
√
√
−
−
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
8-bit
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
16-bit
−
−
√
√
√
√
−
−
−
−
−
−
−
−
√
√
√
√
√
√
√
√
√
√
√
After Reset
Undefined
Undefined
Undefined
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H