UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 837

• Manufacturer Part Number: UPD78F1144AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1144AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Real-time
counter
Watchdog
timer
Function
WDTE:
Watchdog timer
enable register
Controlling
operation
1, 512 Hz and
32.768, 16.384
kHz outputs of
real-time counter
Setting overflow
time
Setting window
open period
Details of
Function
First set RTCEN to 1, while oscillation of the subsystem clock (f
If a value other than “ACH” is written to WDTE, an internal reset signal is generated.
If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset
signal is generated.
The value read from WDTE is 9AH/1AH (this differs from the written value (ACH)).
When data is written to WDTE for the first time after reset release, the watchdog timer
is cleared in any timing regardless of the window open time, as long as the register is
written before the overflow time, and the watchdog timer starts counting again.
If the watchdog timer is cleared by writing “ACH” to WDTE, the actual overflow time
may be different from the overflow time set by the option byte by up to 2/f
The watchdog timer can be cleared immediately before the count value overflows.
The operation of the watchdog timer in the HALT and STOP modes differs as follows
depending on the set value of bit 0 (WDSTBYON) of the option byte (000C0H). (See
the table on page 293.)
If WDSTBYON = 0, the watchdog timer resumes counting after the HALT or STOP
mode is released. At this time, the counter is cleared to 0 and counting starts. When
operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts
operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer
overflow is short, an overflow occurs during the oscillation stabilization time, causing a
reset.
Consequently, set the overflow time in consideration of the oscillation stabilization
time when operating with the X1 oscillation clock and when the watchdog timer is to
be cleared after the STOP mode release by an interval interrupt.
The watchdog timer continues its operation during self-programming of the flash
memory and EEPROM emulation. During processing, the interrupt acknowledge time
is delayed. Set the overflow time and window size taking this delay into
consideration.
The watchdog timer continues its operation during self-programming of the flash
memory and EEPROM emulation. During processing, the interrupt acknowledge time
is delayed.
consideration.
When data is written to WDTE for the first time after reset release, the watchdog
timer is cleared in any timing regardless of the window open time, as long as the
register is written before the overflow time, and the watchdog timer starts counting
again.
The watchdog timer continues its operation during self-programming of the flash
memory and EEPROM emulation. During processing, the interrupt acknowledge
time is delayed.
consideration.
When bit 0 (WDSTBYON) of the option byte (000C0H) = 0, the window open period
is 100% regardless of the values of WINDOW1 and WINDOW0.
Do not set the window open period to 25% if the watchdog timer corresponds to
either of the conditions below.
• When used at a supply voltage (V
• When stopping all main system clocks (internal high-speed oscillation clock, X1
• Low-power consumption mode
clock, and external main system clock) by use of the STOP mode or software.
APPENDIX B LIST OF CAUTIONS
User’s Manual U17854EJ9V0UD
Set the overflow time and window size taking this delay into
Set the overflow time and window size taking this delay into
DD
) below 2.7 V.
Cautions
SUB
) is stable.
IL
seconds.
p.283
p.291
p.291
p.291
p.292
p.292
p.292
p.293
p.293
p.293
p.294
p.294
p.294
p.294
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