UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 842

• Manufacturer Part Number: UPD78F1144AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1144AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

840
Registers
controlling
serial array
unit
Operation
stop mode
3-wire
I/O
CSI10,)
communicatio
n
Function
(CSI00,
serial
SMRmn: Serial
mode register
mn
SCRmn: Serial
communication
operation setting
register mn
SDRmn: Higher
7 bits of the
serial data
register mn
SIRmn: Serial
flag clear trigger
register mn
SSm: Serial
channel start
register m
STm: Serial
channel stop
register m
SOEm: Serial
output enable
register m
SOm: Serial
output register m
SOLm: Serial
output level
register m
ISC: Input switch
control register
NFEN0: Noise
filter enable
register 0
Stopping the
operation by
units
Master
transmission
Master transmission
(in continuous
transmission mode)
Master reception After setting the PER0 register to 1, be sure to set the SPS0 register after 4 or more
Details of
Function
The MD0n0 bit can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it will be rewritten
before the transfer end interrupt of the last transmit data.
Be sure to clear bits 13 to 9, 7, 4, and 3 to “0”. Be sure to set bit 5 to “1”.
Be sure to clear bits 3, 6, and 11 to “0”. Be sure to set bit 2 to “1”.
Be sure to clear bit 8 to “0”.
Setting SDRmn[15:9] = (0000000B, 0000001B) is prohibited when UART is used.
Setting SDR02[15:9] = 0000000B is prohibited when simplified I
SDR02[15:9] to 0000001B or greater.
Do not write eight bits to the lower eight bits if operation is stopped (SEmn = 0). (If
these bits are written to, the higher seven bits are cleared to 0).
Be sure to clear bits 15 to 3 to “0”.
Be sure to clear bits 15 to 4 of SS0, and bits 15 to 4, 1 and 0 of SS1 to “0”.
Be sure to clear bits 15 to 4 of ST0, and bits 15 to 4, 1 and 0 of ST1 to “0”.
Be sure to clear bits 15 to 3 and 1 of SOE0, and bits 15 to 3, 1 and 0 of SOE1 to “0”. p.356
Be sure to set bits 11, 9, 3 and 1 of SO0, and bits 11 to 8, 3, 1 and 0 of SO1 to “1”.
And be sure to clear bits 15 to 12, and 7 to 4 of SOm to “0”.
Be sure to clear bits 15 to 3 and 1 of SOL0, and bits 15 to 3, 1 and 0 of SOL1 to “0”.
Be sure to clear bits 7 to 2 to “0”.
Be sure to clear bits 7, 5, 3, and 1 to “0”.
If SAUmEN = 0, writing to a control register of serial array unit m is ignored, and,
even if the register is read, only the default value is read (except for input switch
control register (ISC), noise filter enable register (NFEN0), port input mode register
(PIM0), port output mode register (POM0), port mode registers (PM0, PM1), and port
registers (P0, P1)).
Be sure to clear bits 1 and 6 of PER0 register to 0.
After setting the PER0 register to 1, be sure to set the SPS0 register after 4 or more
clocks have elapsed.
clocks have elapsed.
APPENDIX B LIST OF CAUTIONS
User’s Manual U17854EJ9V0UD
Cautions
2
C is used. Set
373, 375
381, 383
p.344
pp.346,
347, 348
p.349
p.349
p.349
p.349
p.352
p.354
p.355
p.357
p.358
p.359
p.360
p.363
p.363
pp.369,
p.374
pp.378,
(16/33)
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