UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 846

• Manufacturer Part Number: UPD78F1144AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1144AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

844
DMA
controller
Interrupt
functions
Function
Priority
Response time
Operation in
standby mode
DMA pending
instruction
Operation if
address in
general-purpose
register area or
other than those
of internal RAM
area is specified
IF0L, IF0H, IF1L,
IF1H, IF2L, IF2H:
Interrupt request
flag registers
Details of
Function
During DMA transfer, a request from the other DMA channel is held pending even if
generated. The pending DMA transfer is started after the ongoing DMA transfer is
completed. If two DMA requests are generated at the same time, however, DMA
channel 0 takes priority over DMA channel 1.
If a DMA request and an interrupt request are generated at the same time, the DMA
transfer takes precedence, and then interrupt servicing is executed.
The response time of DMA transfer is as follows. (See Table 14-2.)
The DMA controller operates as follows in the standby mode. (See Table 14-3.)
Even if a DMA request is generated, DMA transfer is held pending immediately after
the following instructions.
• CALL !addr16
• CALL $!addr20
• CALL !!addr20
• CALL rp
• CALLT [addr5]
• BRK
• Bit manipulation instructions for registers IF0L, IF0H, IF1L, IF1H, IF2L, IF2H,
The address indicated by DRA0n is incremented during DMA transfer. If the address
is incremented to an address in the general-purpose register area or exceeds the
area of the internal RAM, the following operation is performed.
In either case, malfunctioning may occur or damage may be done to the system.
Therefore, make sure that the address is within the internal RAM area other than the
general-purpose register area.
Be sure to clear bits 4 to 6 of IF1H and bits 1 to 7 of IF2H to 0.
When operating a timer, serial interface, or A/D converter after standby release,
operate it once after clearing the interrupt request flag. An interrupt request flag may
be set by noise.
When manipulating a flag of the interrupt request flag register, use a 1-bit memory
manipulation instruction (CLR1).
manipulation instruction such as “IF0L.0 = 0;” or “_asm(“clr1 IF0L, 0”);” because the
compiled assembler must be a 1-bit memory manipulation instruction (CLR1).
If a program is described in C language using an 8-bit memory manipulation
instruction such as “IF0L &= 0xfe;” and compiled, it becomes the assembler of three
instructions.
In this case, even if the request flag of another bit of the same interrupt request flag
register (IF0L) is set to 1 at the timing between “mov a, IF0L” and “mov IF0L, a”, the
flag is cleared to 0 at “mov IF0L, a”. Therefore, care must be exercised when using
an 8-bit memory manipulation instruction in C language.
MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, PR00L, PR00H, PR01L, PR01H,
PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H
In mode of transfer from SFR to RAM
The data of that address is lost.
In mode of transfer from RAM to SFR
Undefined data is transferred to SFR.
mov a, IF0L
and a, #0FEH
mov IF0L, a
APPENDIX B LIST OF CAUTIONS
User’s Manual U17854EJ9V0UD
When describing in C language, use a bit
Cautions
p.573
p.574
p.574
p.575
p.575
p.584
p.584
p.584
(20/33)
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