UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 848

• Manufacturer Part Number: UPD78F1144AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1144AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

846
Standby
function
Function
OSTC:
Oscillation
stabilization time
counter status
register
OSTS:
Oscillation
stabilization time
select register
STOP mode
Details of
Function
−
The oscillation stabilization time counter counts up to the oscillation stabilization time
set by OSTS. If the STOP mode is entered and then released while the internal high-
speed oscillation clock is being used as the CPU clock, set the oscillation stabilization
time as follows.
The following sequence is recommended for operating current reduction of the A/D
converter when the standby function is used: First clear bit 7 (ADCS) and bit 0
(ADCE) of the A/D converter mode register (ADM) to 0 to stop the A/D conversion
operation, and then execute the STOP instruction.
It can be selected by the option byte whether the internal low-speed oscillator
continues oscillating or stops in the HALT or STOP mode.
CHAPTER 22 OPTION BYTE.
After the above time has elapsed, the bits are set to 1 in order from MOST8 and
remain 1.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS
before executing the STOP instruction.
Setting the oscillation stabilization time to 20
Before changing the setting of the OSTS register, confirm that the count operation of
the OSTC register is completed.
Do not change the value of the OSTS register during the X1 clock oscillation
stabilization time.
The oscillation stabilization time counter counts up to the oscillation stabilization time
set by OSTS. If the STOP mode is entered and then released while the internal high-
speed oscillation clock is being used as the CPU clock, set the oscillation
stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
Because the interrupt request signal is used to clear the standby mode, if there is an
interrupt source with the interrupt request flag set and the interrupt mask flag reset,
the standby mode is immediately cleared if set. Thus, the STOP mode is reset to the
HALT mode immediately after execution of the STOP instruction and the system
returns to the operating mode as soon as the wait time set using the oscillation
stabilization time select register (OSTS) has elapsed.
To use the peripheral hardware that stops operation in the STOP mode, and the
peripheral hardware for which the clock that stops oscillating in the STOP mode after
the STOP mode is released, restart the peripheral hardware.
To stop the internal low-speed oscillation clock in the STOP mode, use an option
byte to stop the watchdog timer operation in the HALT/STOP mode (bit 0
(WDSTBYON) of 000C0H = 0), and then execute the STOP instruction.
OSTS
OSTS
APPENDIX B LIST OF CAUTIONS
User’s Manual U17854EJ9V0UD
Cautions
μ
s or less is prohibited.
For details, see
p.600
p.600
p.601
p.601
p.602
p.602
p.602
p.602
p.602
p.608
p.610
p.610
p.601
p.602
(22/33)
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