UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 868

• Manufacturer Part Number: UPD78F1144AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1144AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

866
4th edition
(Modification
Version)
5th edition
Edition
Deletion of description of Temperature Correction function of Internal High-Speed
Oscillation Clock and Temperature correction tables H, L from the following chapters.
• CHAPTER 3 CPU ARCHITECTURE
• CHAPTER 5 CLOCK GENERATOR
• CHAPTER 10 A/D CONVERTER
• CHAPTER 12 SERIAL INTERFACE IIC0
• CHAPTER 18 RESET FUNCTION
• CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET)
Deletion of target from the capacitance value of the capacitor connected to the REGC
pin
Change of description in 2.2.15 REGC
Modification of P60 to P64 in Table 2-2 Connection of Unused Pins
Addition (address change) of the BCDADJ register to Table 3-6 Extended SFR (2nd
SFR) List (1/4)
Change of Figure 4-34 Bit Manipulation Instruction (P10)
Change of Caution 2 in Figure 5-6 Format of System Clock Control Register
(CKC)
Change of description in 5.3 (8) Internal high-speed oscillator trimming register
(HIOTRM) and addition of Caution
Change of Figure 5-9 Format of Internal High-Speed Oscillator Trimming
Register (HIOTRM) and addition of Caution
Change of Figure 5-13 Clock Generator Operation When Power Supply Voltage
Is Turned On (When LVI Default Start Function Stopped Is Set (Option Byte:
LVIOFF = 1))
Addition of Note to Figure 6-5 Format of Timer Clock Select Register 0 (TPS0)
Change of Table 6-3 OVF Bit Operation and Set/Clear Conditions in Each
Operation Mode and addition of Remark
Addition of Caution 2 to Figure 6-18. Format of Timer Output Register 0 (TO0)
Change of description in 6.3 (14) Noise filter enable register 1 (NFEN1)
Change of 6.5.1 TI0n edge detection circuit
Change of Figure 7-1 Block Diagram of Real-Time Counter
Addition of Caution 3 to Table 8-4 Setting Window Open Period of Watchdog
Timer
Fixing of the SOE01 and SOEm3 bit settings to “0”.
Fixing of the SO10, SOm1, SOm3, CKO10, CKOm1, CKO12, and CKOm3 bit settings
to “1”.
Change of “Setting disabled (set to the initial value)” in Remark
Change of Figure 11-1 Block Diagram of Serial Array Unit 0
Change of Figure 11-2 Block Diagram of Serial Array Unit 1
Addition of settings and Note to Figure 11-5 Format of Serial Clock Select
Register m (SPSm)
Change of Figure 11-11 Format of Serial Channel Enable Status Register m
(SEm)
Change of Figure 11-14 Format of Serial Output Enable Register m (SOEm)
Addition of description to 11.3 (12) Serial output register m (SOm)
APPENDIX C REVISION HISTORY
User’s Manual U17854EJ9V0UD
Description
Throughout
Throughout
CHAPTER 2 PIN
FUNCTIONS
CHAPTER 3 CPU
ARCHITECTURE
CHAPTER 4 PORT
FUNCTIONS
CHAPTER 5 CLOCK
GENERATOR
CHAPTER 6 TIMER
ARRAY UNIT
CHAPTER 7 REAL-
TIME COUNTER
CHAPTER 8
WATCHDOG TIMER
CHAPTER 11 SERIAL
ARRAY UNIT
Chapter
(4/15)