UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 870

• Manufacturer Part Number: UPD78F1144AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1144AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

868
5th edition
6th edition
Edition
Additions of Note 3 to Figure 20-8 Timing of Low-Voltage Detector Interrupt
Signal Generation (Bit: LVISEL = 0, Option Byte: LVIOFF = 1)
Change of description and Caution in 20.4.2 (1) (b)
Change of Figure 20-9 Timing of Low-Voltage Detector Interrupt Signal
Generation (Bit: LVISEL = 0, Option Byte: LVIOFF = 0) and addition of Note
Change of <4> in 20.4.2 (2)
Change of Figure 20-10 Timing of Low-Voltage Detector Interrupt Signal
Generation (Bit: LVISEL = 1) and addition of Note 3
Change of Figure 20-11 Example of Software Processing After Reset Release
Change of 21.1 Regulator Overview
Addition of Note 3 to Figure 21-1 Format of Regulator Mode Control Register
(RMC)
Change of description in 22.1.1 (2) 000C1H/010C1H
Change of Figure 22-2 Format of User Option Byte (000C1H/010C1H) and
Caution 2
Change of description in 23.4.5 REGC pin
Addition of Caution 4 to 23.8 Flash Memory Programming by Self-Programming
Addition of 24.3 Securing of user resources
Modification of throughout
Addition of package and Note to 1.3 Ordering Information
Addition of package and Note to 1.4 Pin Configuration (Top View)
Change of 1.7 Outline of Functions
Change of corresponding pins of EV
Supplies
Change of description in 2.2.15 REGC
Change of description in 2.2.18 FLMD0
Modification of 37-A to 37-B and 39 to 2-W in Table 2-2. Connection of Unused
Pins
Modification of 37-A to 37-B and 39 to 2-W in Figure 2-1. Pin I/O Circuit List
Change of address in Figure 3-16. Configuration of General-Purpose Registers
Addition of register and Note in Table 3-5. SFR List
Addition of PIM register and POM register in block diagram
Change of corresponding pins of EV
Supplies
Change of Cautions 1 and Cautions 2 in 4.2.1 Port 0
Change of Cautions 1, Cautions 2, and Cautions 3 in 4.2.2 Port 1
Change of Cautions 1 and addition of Cautions 2 in 4.2.4 Port 3
Change of Cautions 2 in 4.2.5 Port 4
Addition of Caution to 4.2.7 Port 6
Addition of Caution to 4.2.11 Port 14
Addition description to (4) Port input mode registers (PIM0) and (5) Port output
mode registers (POM0) in 4.3
Change of Figure 4-32. Format of Port Input Mode Register
APPENDIX C REVISION HISTORY
User’s Manual U17854EJ9V0UD
DD
DD
Description
and V
and V
DD
DD
in Table 2-1. Pin I/O Buffer Power
in Table 4-1. Pin I/O Buffer Power
CHAPTER 20 LOW-
VOLTAGE DETECTOR
CHAPTER 21
REGULATOR
CHAPTER 22 OPTION
BYTE
CHAPTER 23 FLASH
MEMORY
CHAPTER 24 ON-CHIP
DEBUGGING
CHAPTER 27
ELECTRICAL
SPECIFICATIONS
(TARGET)
CHAPTER 1 OUTLINE
CHAPTER 2 PIN
FUNCTIONS
CHAPTER 3 CPU
ARCHITECTURE
CHAPTER 4 PORT
FUNCTIONS
Chapter
(6/15)