UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 876

• Manufacturer Part Number: UPD78F1144AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1144AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

874
8th edition
Edition
Addition of Note to 11.1.3 Simplified I
Change of Note 2 in Figure 11-5 Format of Serial Clock Select Register m (SPSm)
Change of Figure 11-7 Format of Serial Communication Operation Setting
Register mn (SCRmn)
Change of Figure 11-26 Procedure for Stopping Master Transmission
Change of Figure 11-28 Timing Chart of Master Transmission (in Single-
Transmission Mode) (Type 1: DAP0n = 0, CKP0n = 0)
Change of Figure 11-30 Timing Chart of Master Transmission (in Continuous
Transmission Mode) (Type 1: DAP0n = 0, CKP0n = 0)
Change of (b) Serial output enable register 0 (SOE0) in Figure 11-32. Example of
Contents of Registers for Master Reception of 3-Wire Serial I/O (CSI00, CSI10)
Modification of Figure 11-36 Timing Chart of Master Reception (in Single-
Reception Mode) (Type 1: DAP0n = 0, CKP0n = 0)
Change of Figure 11-40 Procedure for Stopping Master Transmission/Reception
Modification of Figure 11-42 Timing Chart of Master Transmission/Reception (in
Single-Transmission/Reception Mode) (Type 1: DAP0n = 0, CKP0n = 0)
Modification of Figure 11-44 Timing Chart of Master Transmission/Reception (in
Continuous Transmission/Reception Mode) (Type 1: DAP0n = 0, CKP0n = 0)
Change of transfer rate in 11.5.4 Slave transmission
Change of Figure 11-48 Procedure for Stopping Slave Transmission
Change of Figure 11-50 Timing Chart of Slave Transmission (in Single-
Transmission Mode) (Type 1: DAP0n = 0, CKP0n = 0)
Change of Figure 11-52 Timing Chart of Slave Transmission (in Continuous
Transmission Mode) (Type 1: DAP0n = 0, CKP0n = 0)
Change of Figure 11-53 Flowchart of Slave Transmission (in Continuous
Transmission Mode)
Change of transfer rate in 11.5.5 Slave reception
Change of (b) Serial output enable register 0 (SOE0) in Figure 11-54. Example of
Contents of Registers for Slave Reception of 3-Wire Serial I/O (CSI00, CSI10)
Modification of Figure 11-58 Timing Chart of Slave Reception (in Single-
Reception Mode) (Type 1: DAP0n = 0, CKP0n = 0)
Change of transfer rate in 11.5.6 Slave transmission/reception
Change of Figure 11-62 Procedure for Stopping Slave Transmission/Reception
Change of Figure 11-63 Procedure for Resuming Slave Transmission/Reception
Modification of Figure 11-64 Timing Chart of Slave Transmission/Reception (in
Single-Transmission/Reception Mode) (Type 1: DAP0n = 0, CKP0n = 0)
Modification of Figure 11-66 Timing Chart of Slave Transmission/Reception (in
Continuous Transmission/Reception Mode) (Type 1: DAP0n = 0, CKP0n = 0)
Change of Note 2 in Table 11-2 Selection of Operation Clock
Addition of Caution to 11.6 Operation of UART (UART0, UART1, UART3)
Communication
Change of Figure 11-70 Procedure for Stopping UART Transmission
Change of Figure 11-72 Timing Chart of UART Transmission (in Single-
Transmission Mode)
Change of Figure 11-74 Timing Chart of UART Transmission (in Continuous
Transmission Mode)
Change of 11.6.2 UART reception
APPENDIX C REVISION HISTORY
User’s Manual U17854EJ9V0UD
Description
2
C (IIC10)
CHAPTER 11 SERIAL
ARRAY UNIT
Chapter
(12/15)