UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 877

• Manufacturer Part Number: UPD78F1144AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1144AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8th edition
Edition
Modification of Figure 11-80 Timing Chart of UART Reception
Modification of transfer data length in 11.6.3 LIN transmission
Change of Note 2 in Figure 11-82 Transmission Operation of LIN
Modification of transfer data length in 11.6.4 LIN reception
Change of Note 2 in Table 11-3 Selection of Operation Clock
Addition of Note to 11.7 Operation of Simplified I
Addition of Note to 11.7.1 Address field transmission
Change of Figure 11-89 Initial Setting Procedure for Address Field Transmission
Change of Figure 11-90 Timing Chart of Address Field Transmission
Addition of Note to 11.7.2 Data transmission
Change of Figure 11-93 Timing Chart of Data Transmission
Addition of Note to 11.7.3 Data reception
Change of Figure 11-96 Timing Chart of Data Reception
Change of Figure 11-97 Flowchart of Data Reception and change of Caution
Change of Figure 11-98 Timing Chart of Stop Condition Generation
Change of Note 2 in Table 11-4 Selection of Operation Clock
Change of Note in Figure 12-6 Format of IIC Control Register 0 (IICC0)
Change of Table 12-2 Selection Clock Setting
Change of Table 12-3 Selection Clock Setting
Change of Table 12-5 Extension Code Bit Definitions
Change of Figure 12-24 Master Operation in Single-Master System
Change of Figure 12-25 Master Operation in Multi-Master System
Change of Figure 12-26 Slave Operation Flowchart
Change of Figures 12-28 and 12-29
Change of Figure 14-5 Format of DMA Operation Control Register n (DRCn)
Addition of Note to Table 14-2 Response Time of DMA Transfer
Change of description in 15.2 Interrupt Sources and Configuration
Change of Table 15-1 Interrupt Source List
Change of Caution 2 in 16.3 (1) Key return mode register (KRM)
Change of Note in Figure 17-3 HALT Mode Release by Interrupt Request
Generation
Change of Figure 17-5 Operation Timing When STOP Mode Is Released (Release
by Unmasked Interrupt Request)
Addition of Note to Figure 17-6 STOP Mode Release by Interrupt Request
Generation
Deletion of Note in 19.1 Functions of Power-on-Clear Circuit
Deletion of Note in 19.3 Operation of Power-on-Clear Circuit
Deletion of Note 6 in (1) When LVI is OFF upon power application (option byte:
LVIOFF = 1) in Figure 19-2 Timing of Generation of Internal Reset Signal by
Power-on-Clear Circuit and Low-Voltage Detector
Deletion of Note 3 in (2) When LVI is ON upon power application (option byte:
LVIOFF = 0) in Figure 19-2 Timing of Generation of Internal Reset Signal by
Power-on-Clear Circuit and Low-Voltage Detector
APPENDIX C REVISION HISTORY
User’s Manual U17854EJ9V0UD
Description
2
C (IIC10) Communication
CHAPTER 11 SERIAL
ARRAY UNIT
CHAPTER 12 SERIAL
INTERFACE IIC0
CHAPTER 14 DMA
CONTROLLER
CHAPTER 15
INTERRUPT
FUNCTIONS
CHAPTER 16 KEY
INTERRUPT FUNCTION
CHAPTER 17
STANDBY FUNCTION
CHAPTER 19 POWER-
ON-CLEAR CIRCUIT
Chapter
(13/15)
875