SAB-C161S-L25M AA Infineon Technologies, SAB-C161S-L25M AA Datasheet - Page 50

• Manufacturer Part Number: SAB-C161S-L25M AA
• Description: IC MICROCONTROLLER 16BIT MQFP80
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAB-C161S-L25M AA

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-SQFP
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: ASC, SSC
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 63
• Number Of Timers: 5
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Packages: PG-MQFP-80
• Max Clock Frequency: 25.0 MHz
• Sram (incl. Cache): 2.0 KByte
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: B161SL25MAAXT; SABC161SL25MAAXT; SP000014739

The timings listed in the AC Characteristics that refer to TCLs therefore must be
calculated using the minimum TCL that is possible under the respective circumstances.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCL is lower than
for one single TCL (see formula and
For a period of N
deviation D
(N
where N = number of consecutive TCLs and 1
So for a period of 3 TCLs @ 20 MHz (i.e. N = 3): D
and (3TCL)
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
Note: For all periods longer than 40 TCL the N = 40 value can be used (see
Figure 11
Data Sheet
Max. jitter
TCL)
±26.5
±30
±20
±10
±1
D
ns
min
N
N
min
:
= N
1
Approximated Maximum Accumulated PLL Jitter
= 3TCL
This approximated formula is valid for
1
< –
TCL
N
TCL the minimum value is computed using the corresponding
< –
NOM
40 and 10 MHz
NOM
- 1.61 ns = 73.39 ns (@
10
- D
N
, D
N
< –
[ns] = (13.3 + N
Figure
f
CPU
20
< –
46
25 MHz.
11).
N
f
3
CPU
= (13.3 + 3
40.
30
= 20 MHz).
6.3) /
f
CPU
Timing Characteristics
6.3) / 20 = 1.61 ns,
[MHz]
40
V1.0, 2003-11
Figure
MCD04455
10 MHz
16 MHz
20 MHz
25 MHz
C161S
11).
N
(1)