SAB-C161S-L25M AA Infineon Technologies, SAB-C161S-L25M AA Datasheet - Page 66

• Manufacturer Part Number: SAB-C161S-L25M AA
• Description: IC MICROCONTROLLER 16BIT MQFP80
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAB-C161S-L25M AA

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-SQFP
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: ASC, SSC
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 63
• Number Of Timers: 5
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Packages: PG-MQFP-80
• Max Clock Frequency: 25.0 MHz
• Sram (incl. Cache): 2.0 KByte
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: B161SL25MAAXT; SABC161SL25MAAXT; SP000014739

Table 18
ALE cycle time = 4 TCL + 2
Parameter
Data float after RdCS
(no RW-delay)
Address hold after
RdCS, WrCS
Data hold after WrCS
1) RW-delay and
2) Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
3) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
Data Sheet
Therefore address changes before the end of RD have no impact on read cycles.
specified together with the address and signal BHE (see figures below).
Demultiplexed Bus (Standard Supply Voltage Range) (cont’d)
(Operating Conditions apply)
t
1)
A
refer to the next following bus cycle (including an access to an on-chip X-Peripheral).
Symbol
t
t
t
68
55
57
t
A
+
t
C
SR –
CC -6 +
CC 6 +
+
t
F
Min.
Max. CPU Clock
(80 ns at 25 MHz CPU clock without waitstates)
t
= 25 MHz
F
62
t
F
Max.
0 +
–
–
t
F
1 / 2TCL = 1 to 25 MHz
Min.
–
-6 +
TCL - 14
+
Variable CPU Clock
t
F
t
F
Timing Characteristics
Max.
TCL - 20
+ 2
–
–
t
A
V1.0, 2003-11
+
t
F
1)
C161S
Unit
ns
ns
ns