MAXQ3108-FFN+ Maxim Integrated Products, MAXQ3108-FFN+ Datasheet
MAXQ3108-FFN+
Specifications of MAXQ3108-FFN+
Related parts for MAXQ3108-FFN+
MAXQ3108-FFN+ Summary of contents
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... Features Independent Watchdog Timer for Each Core External Interrupts JTAG Interface ♦ Operating Modes Stop Mode: 0.1µA typ Active Current at 10MHz and V PART MAXQ3108-FFN+ + Denotes a lead(Pb)-free/RoHS-compliant package. Pin Configuration appears at end of data sheet. ) Data SRAM BAT 2 C Master ) BAT = 2 ...
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Low-Power, Dual-Core Microcontroller Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Figure 1. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Figure 2. IR Option on UART .56 Figure 3. ADC Bit Stream Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Figure 4. Connecting the MAXQ3108 to a DS8102 Dual Delta-Sigma Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Table 1. UserCore Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Table 2. UserCore Peripheral Register Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Table 3. DSPCore Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Table 4. DSPCore Peripheral Register Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 5 ...
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Low-Power, Dual-Core Microcontroller ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin except V with Respect to V ...........................-0. Voltage Range on V with Respect Operating Temperature Range ...........................-40°C to +85°C Stresses beyond those ...
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Low-Power, Dual-Core Microcontroller RECOMMENDED DC OPERATING CONDITIONS (continued 3.6V -40°C to +85°C.) (Notes RST A PARAMETER SYMBOL Input/Output Pin Capacitance Input Low Current All Pins Input-Leakage Current Input Pullup Resistor (All ...
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... RESULT MAXQ20 DSPCORE 24-BIT RESULT 4kW SRAM (CODE) 512W SRAM (DATA) 24-BIT RESULT MULTIPLY- ACCUMULATE 24-BIT RESULT UNIT MAILBOX COMM 1.8V CORE LDO AND SUPPLY MONITOR 32kHz FLL OSC RTC MAXQ3108 P2.5/CF1 P2.6/CF2 V DD GND REGOUT P1.6/RST V BAT CX1 CX2 ...
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Low-Power, Dual-Core Microcontroller PIN NAME Supply Voltage. Must be bypassed with a 4.7μF capacitor with ESR < capacitor. 17 GND Ground Regulator Output. 1.8V output. Must be connected to a 1μF low-ESR (< external ...
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... C masters, real-time clock, programmable pulse generators, dual UARTs (one of which that supports IR carrier frequency modulation), and math accelerators. At the heart of the MAXQ3108 are two MAXQ20 16-bit RISC microcontrollers. The dual-core approach allows one core (DSPCore entirely dedicated to collec- tion and processing of AFE samples for the metering function, while the second core handles any communi- cation and user-specific administrative functions ...
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... Memory is accessed through specific data pointer registers with auto increment/decrement support. The MAXQ3108 supports a pseudo-Von Neumann memory structure that can merge program and data into a linear memory map. This is accomplished by mapping the data memory into the program space or mapping the program memory segment into the data space ...
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... The MAXQ3108 UserCore implements the standard set of system registers as described in the MAXQ Family User’s Guide . The exceptions are listed below: • In the IMR register, bit IM5 is not implemented since there is no module 5 implemented in the MAXQ3108. Table 1. UserCore Peripheral Registers MOD: REGISTER ...
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Low-Power, Dual-Core Microcontroller Table 1. UserCore Peripheral Registers (continued) MOD: REGISTER REG AD1LSB 0:9 AD2LSB 0:10 AD3LSB 0:11 AD4LSB 0:12 AD5LSB 0:13 MREQ0 0:14 MREQ1 0:15 MREQ2 0:16 ADCN 0:17 IF54E IF32E IFCSEL ADCC 0:18 MSTC 0:19 ...
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Low-Power, Dual-Core Microcontroller Table 1. UserCore Peripheral Registers (continued) MOD: REGISTER REG T2RH 2:2 T2CH 2:3 PO2 2:4 PI2 2:5 SCON0 2:6 SBUF0 2:7 SMD0 2:8 PR0 2:9 PD2 2:10 T2CNB 2:11 T2V 2:12 T2R 2:13 T2C ...
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Low-Power, Dual-Core Microcontroller Table 2. UserCore Peripheral Register Default Values MOD: REGISTER REG AD0 0:0 AD1 0:1 AD2 0:2 AD3 0:3 AD4 0:4 AD5 0:5 SRSP0 0:6 SRSP1 0:7 AD0LSB 0:8 AD1LSB 0:9 AD2LSB 0:10 AD3LSB 0:11 ...
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Low-Power, Dual-Core Microcontroller Table 2. UserCore Peripheral Register Default Values (continued) MOD: REGISTER REG RCNT 1: RTSS 1:26 RTSH 1:27 RTSL 1:28 RSSA 1:29 RASH 1:30 RASL 1:31 T2CNA 2:0 T2H 2:1 T2RH 2:2 ...
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... REG TB0V 4:11 I2CCN 4:12 0 I2CCK 4:13 I2CTO 4:14 I2CSLA 4:15 Peripheral Registers—DSPCore The MAXQ3108 DSPCore exposes its peripheral com- plement in modules numbered 0 and 1. Table 3 Table 3. DSPCore Peripheral Registers MOD: REGISTER REG AD0 0:0 AD1 0:1 AD2 0:2 AD3 0:3 ...
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Low-Power, Dual-Core Microcontroller Table 3. DSPCore Peripheral Registers (continued) MOD: REGISTER REG PO2 1:7 MC1R 1:8 MC0R 1:9 CF1D 1:12 CF2D 1:13 Table 4. DSPCore Peripheral Register Default Values MOD: REGISTER REG AD0 0:0 ...
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Low-Power, Dual-Core Microcontroller REGISTER AD0 (00h, 00h) Analog-to-Digital Converter 0 Output Register Initialization: This register is reset to 0xFFFF on all forms of reset. Read/Write Access: Unrestricted read access. Analog-to-Digital Converter 0 Output Register. This register contains the most significant ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued) SRSP1 (07h, 00h) Slave Response Register 1 Initialization: This register is reset to 0000h on all forms of reset. Read/Write Access: Unrestricted read access only to the UserCore. Unrestricted read/write access ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued) MREQ1 (0Fh, 00h) Master Request Register 1 Initialization: This register is reset to 0000h on all forms of reset. Read/Write Access: Unrestricted read/write access only to the UserCore. Unrestricted read access ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued) ADC5 Buffer Full Flag. This bit is set by hardware to indicate that a sample is available from ADC5. An interrupt request is generated to a CPU if IF45E = 1 ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued) ADC Interrupt Flags 3 and 2 Enable. This bit serves as the local interrupt enable for the ADC cubic ADCN.13: IF32E sinc filter output buffers 3 and 2. ADC Interrupt Flags ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued) Clock Correction Hardware Selection Bits 1:0. These bits are used to enable and assign the clock measurement hardware to one of the three Manchester decoders. When these bits are 11b, the ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued) PI0 (02h, 01h) Port 0 Input Register Initialization: The reset value for this register is dependent on the logical states of the pins. Read/Write Access: Unrestricted read-only. Port 0 Input Register ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued) EIE1 (07h, 01h) External Interrupt Enable 1 Register Initialization: EIE1 is cleared to 00h on all forms of reset. Read/Write Access: Unrestricted read/write. Enable External Interrupt Bits 11:8. Setting any of ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued) EIES1 (0Bh, 01h) External Interrupt Edge Select 1 Register Initialization: EIES1 is cleared to 00h on all forms of reset. Read/Write Access: Unrestricted read/write. External Interrupt Edge Select Bits 11:8 ITx ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued) FCNTL (0Dh, 01h) Flash Memory Control Register Initialization: This register is set to 80h on POR and is unaffected by all other forms of reset. Unrestricted read, bits 2:0 are write ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued) Enable Clock Output Pin. Setting this bit to 1 enables the output of the DSPCore undivided system clock on P2.2. The P2.2 pin also serves as the SPI serial clock (SCLK) ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued) RTRM (18h, 01h) Real-Time Clock Trim Register (8-Bit Register) Initialization: This register is battery backed through POR so long indeterminate on the very first POR and must be ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued) Alarm Time-of-Day Flag. This bit is set when the contents of RTSH and RTSL counter registers match the 20-bit value in the RASH and RASL alarm registers. Setting the ALDF causes ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued) RTSS (1Ah, 01h) RTC Subsecond Counter Register (8-Bit Register) Initialization: This register is battery backed through POR so long indeterminate on the very first POR and must be ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued) RASH (1Eh, 01h) RTC Alarm Time-of-Day High Register (8-Bit Register) Initialization: This register is battery backed through POR so long indeterminate on the very first POR and must ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued) Single Shot. This bit is used to automatically override or delay the effect of the TR2 bit setting. The single-shot bit is only useful in the timer mode of operation (C/T2 ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued) Timer 2 Output Enable 0. This register bit enables the timer 2 output function for the external T2P pin. The table below shows timer 2 output possibilities for the T2P, T2PB ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued) PI2 (05h, 02h) Port 2 Input Register Initialization: The reset value for this register is dependent on the logical states of the pins. Read/Write Access: Unrestricted read-only. Port 2 Input Register ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued) Serial Port 0 Mode Bit 0/Framing Error Flag. When FEDE is 0, this is the SM0 bit. When FEDE is set to 1, this bit is the FE that is set ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued) Enable TXD PWM Output Function. Setting this bit enables the output of the logical function selected by the OFS bit to be output on the TXD0 pin for ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued) Timer 2 Output Enable 1. See the table given under T2CNA.6 bit description. The T2OE1 bit is not T2CNB.6: T2OE1 implemented for single pin versions of timer 2. Enable Timer 2 ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued) Timer 2 Capture/Compare Function Select. These bits, in conjunction with the C/T2 bit, select the basic operating mode of timer 2. In the dual 8-bit mode of operation (T2MD = 1), ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued) Multiply-Accumulate Negate. The state of the MSUB and MMAC bits determines the operation of the hardware multiplier. The accumulator MC is formed by the MC2, MC1, and MC0 registers. MCNT.2: MSUB ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued) MB (02h, 03h) Multiplier Operand B Register Initialization: This register is cleared to 0000h on all forms of reset. Read/Write Access: Unrestricted read/write. Multiplier Operand B Bit 15:0. This operand B ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued) MC0R (09h, 03h) Multiplier Read Register 0 Initialization: This register is cleared to 0000h on all forms of reset. Read/Write Access: Unrestricted read-only. Multiplier Read Register 0 Bit 15:0. During multiplication, ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued) SPICF (0Eh, 03h) SPI Configuration Register Initialization: This buffer is cleared to 00h on all forms of reset. Read/Write Access: Unrestricted read/write. Clock Polarity Select. This bit is used with the ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued Transmit Complete Interrupt Flag. This bit indicates that an address or a data byte has been successfully shifted out and the I I2CST.1: I2CTXI (NACK or ACK). This ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued) 2 I2CIE (02h, 04h Interrupt Enable Register (16-Bit Register) Initialization: This register is cleared to 0000h on all forms of reset. Read/Write Access: Unrestricted read/write access ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued) TB0C (05h, 04h) Timer B 0 Compare Initialization: This register is cleared to 0000h on all forms of reset. Read/Write Access: Unrestricted read/write. Timer B Compare Bits 15:0. This register is ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued) SMD1 (08h, 04h) Serial Port Mode Register 1 Initialization: This register is cleared to 00h on all forms of reset. Read/Write Access: Unrestricted read/write. Framing-Error-Detection Enable. This bit selects the function ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued) Timer B Output Enable. Setting this bit to 1 enables the clock output function on the TBA pin if TB0CN.5: TBOE C/ Timer B rollovers do not cause interrupts. ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued) 2 I2CCN (0Ch, 04h Control Register (16-Bit Register) Initialization: This register is cleared to 0000h on all forms of reset. The I2CSTART and I2CSTOP bits are reset to 0 ...
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Low-Power, Dual-Core Microcontroller Special Function Register Bit Descriptions (continued STOP Enable. Setting this bit to 1 generates a STOP condition. This bit is automatically self- cleared to 0 after the STOP condition has been generated. In master ...
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... C controller automatically acknowledges the 2 C module is enabled (I2CEN = 1). The I2CAMI flag is Peripherals Most of the peripheral devices on the MAXQ3108 require connections to other components. To minimize the pin count, some peripherals share pins with other peripherals. Obviously, only one peripheral can drive a pin at any given time. Table 5 provides information on how to use these multipurpose pins ...
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... This is an active-low reset pin. Driving a low level on P1.6 causes the — MAXQ3108 to reset. The reset function on this pin can be disabled by setting RSTD to 1. — When Manchester decoder 0 is enabled, set P2 input. ...
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... Internal clocks are generated directly from the system clock. Normally, the system clock is sourced from one of the two clock sources. The effect of the PMME and CD bits on the system clock in the MAXQ3108 is sum- marized in Table 6. When the 32,768Hz clock is selected as the system ...
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... Low-Power, Dual-Core Microcontroller Table 6. MAXQ3108 Clock Divisors PMME CD[1: modes. The two power-management modes reduce speed and power consumption by either internally dividing the clock signal by 256 or using the 32kHz clock directly. The stop mode stops all internal clocks (with the exception of the 32kHz crystal amplifier) resulting in a static condition and providing the lowest power state ...
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... Reset places the processor in a reset state and clears the IDLE bit. The DSPCore reset state could result from a global system reset or from clearing of the ENDSP bit by the UserCore. The MAXQ3108 has four ways of entering a reset state: • Power-on reset • Watchdog timer reset • External reset • ...
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... If a reset state is applied while the processor is in stop mode, the reset causes the processor to exit the stop mode and forces the program counter to 8000h. The external reset (RST) pin function on the MAXQ3108 can be disabled by user application code. The power- on-reset default condition is for the RST pin to be enabled ...
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... EPWM = 0 EPWM = 1, OFS = 0 EPWM = 1, OFS = 1 Figure 2. IR Option on UART 0 UART channel 0 on the MAXQ3108 contains a special feature that eases its use with some infrared communi- cation systems. In these systems, an asynchronous ser- ial signal is used to on-off modulate a high-frequency carrier signal. This modulated carrier is then used to further modulate an IR beam ...
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... I2CSLA: Establishes the slave address for the I peripheral. ______________________________________________________________________________________ Use Scenario: MAXQ3108 Master Sends 2 Bytes to Slave 1) Set the I2CEN and I2CMST bits in the I2CCN regis- ter. This enables the I the MAXQ3108 as master. 2) Set the I2CSTART bit in the I2CCN register. This causes the MAXQ3108 to send the START sequence ...
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... Set the slave address in the I2CSLA register. 3) Monitor I2CST. As conditions change on the I bus, they are reflected in the I2CST register. When the I2CAMI bit is set, the address of the MAXQ3108 has been matched. The MAXQ3108 automatically sends ACK when an address matches. 4) Set the I2CACK bit ACK the received bytes. ...
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... The DS8102 is designed to operate with the Manchester data inputs of the MAXQ3108. Figure 4 demonstrates how simple the physical interface can be: just connect the MNOUT pin of the DS8102 to the Figure 4. Connecting the MAXQ3108 to a DS8102 Dual Delta-Sigma Modulator ______________________________________________________________________________________ ADC Registers MDIN0P input of the MAXQ3108, and establish a com- mon ground using the MDIN0N pin ...
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Low-Power, Dual-Core Microcontroller DSPCore uses 8KB (4K instruction words) of RAM as code memory, with a separate 1KB (512 word) data space. Code memory for the DSPCore is implemented as an 8KB block of static RAM. Following power-on reset, the ...
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Low-Power, Dual-Core Microcontroller MREQ0 register. It decodes the request as a RAM read request (0x02.) In response, it reads MREQ1 for the address to read. 4) The DSPCore completes the RAM read operation. 5) The DSPCore loads the results of ...
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... In the MAXQ3108, the counter is 22 bits wide, but only the high-order 16 bits are writable. The other 6 bits are cleared on any write. Thus, the maximum value that can be written to the register is 0x3FFFC0, or, at the default clock rate of the DSPCore (10 ...
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... This MAXQ3108 data sheet, which contains electri- cal/timing specifications and pin descriptions. • The MAXQ3108 errata sheet for the specific device revision, available at www.maxim-ic.com/errata. • The MAXQ Family User's Guide , which contains detailed information on core features and operation, including programming ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 64 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products TOP VIEW MAXQ3108 6 7 P2.5/CF1 8 P2.6/CF2 ...