UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet
UPD78F0386GK-8EU-A
Specifications of UPD78F0386GK-8EU-A
Related parts for UPD78F0386GK-8EU-A
UPD78F0386GK-8EU-A Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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User’s Manual 78K0/LF2 8-Bit Single-Chip Microcontrollers With LCD Controller/Driver PD78F0372 PD78F0373 PD78F0374 PD78F0375 PD78F0376 PD78F0376D Document No. U17504EJ2V0UD00 (2nd edition) Date Published August 2006 NS CP(K) 2005 Printed in Japan PD78F0382 PD78F0383 PD78F0384 PD78F0385 PD78F0386 PD78F0386D ...
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User’s Manual U17504EJ2V0UD ...
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NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care ...
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EEPROM is a trademark of NEC Electronics Corporation. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/ trademark of International Business Machines Corporation. HP9000 series 700 ...
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Caution: This product uses SuperFlash The information in this document is current as of August, 2006. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, ...
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Readers This manual is intended for user engineers who wish to understand the functions of the 78K0/LF2 and design and develop application systems and programs for these devices. The target products are as follows. 78K0/LF2: Purpose This manual is intended ...
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Conventions Data significance: Active low representations: Note: Caution: Remark: Numerical representations: Binary Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices 78K0/LF2 User’s Manual ...
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Other Documents SEMICONDUCTOR SELECTION GUIDE Semiconductor Device Mount Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Note See the “Semiconductor Device Mount Manual” website ...
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CHAPTER 1 OUTLINE ............................................................................................................................ 17 1.1 Features ........................................................................................................................................ 17 1.2 Applications.................................................................................................................................. 18 1.3 Ordering Information ................................................................................................................... 19 1.4 Pin Configuration (Top View)...................................................................................................... 20 1.5 78K0/Lx2 Series Lineup............................................................................................................... 23 1.6 Block Diagram .............................................................................................................................. 25 1.7 Outline of Functions ( PD78F037x) ........................................................................................... ...
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General-purpose registers .............................................................................................................. 63 3.2.3 Special function registers (SFRs).................................................................................................... 64 3.3 Instruction Address Addressing................................................................................................. 69 3.3.1 Relative addressing......................................................................................................................... 69 3.3.2 Immediate addressing..................................................................................................................... 70 3.3.3 Table indirect addressing ................................................................................................................ 71 3.3.4 Register addressing ........................................................................................................................ 71 3.4 Operand Address Addressing .................................................................................................... ...
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X1 oscillator ...................................................................................................................................127 5.4.2 XT1 oscillator .................................................................................................................................127 5.4.3 When subsystem clock is not used ................................................................................................130 5.4.4 Internal high-speed oscillator .........................................................................................................130 5.4.5 Internal low-speed oscillator ..........................................................................................................130 5.4.6 Prescaler........................................................................................................................................130 5.5 Clock Generator Operation ....................................................................................................... 131 5.6 Controlling Clock ....................................................................................................................... 134 5.6.1 ...
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Operation of 8-Bit Timers H0 and H1........................................................................................ 219 8.4.1 Operation as interval timer/square-wave output.............................................................................219 8.4.2 Operation as PWM output ..............................................................................................................222 8.4.3 Carrier generator operation (8-bit timer H1 only)............................................................................228 CHAPTER 9 WATCH TIMER................................................................................................................ 235 9.1 Functions of Watch Timer ......................................................................................................... ...
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Asynchronous serial interface (UART) mode ...............................................................................284 13.4.3 Dedicated baud rate generator ....................................................................................................290 CHAPTER 14 SERIAL INTERFACE UART6 ...................................................................................... 295 14.1 Functions of Serial Interface UART6...................................................................................... 295 14.2 Configuration of Serial Interface UART6 ............................................................................... 299 14.3 Registers Controlling Serial Interface ...
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Write operation.............................................................................................................................421 16.7.3 Read operation.............................................................................................................................424 16.7.3 Read operation.............................................................................................................................424 CHAPTER 17 LCD CONTROLLER/DRIVER ....................................................................................... 428 17.1 Functions of LCD Controller/Driver........................................................................................ 428 17.2 Configuration of LCD Controller/Driver ................................................................................. 430 17.3 Registers Controlling LCD Controller/Driver......................................................................... 433 17.4 Setting LCD Controller/Driver ................................................................................................. 439 ...
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Standby Function and Configuration..................................................................................... 493 21.1.1 Standby function ..........................................................................................................................493 21.1.2 Registers controlling standby function .........................................................................................493 21.2 Standby Function Operation................................................................................................... 496 21.2.1 HALT mode..................................................................................................................................496 21.2.2 STOP mode .................................................................................................................................501 CHAPTER 22 RESET FUNCTION ....................................................................................................... 506 22.1 Register for Confirming Reset Source................................................................................... ...
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Selecting communication mode ...................................................................................................556 26.7.4 Communication commands..........................................................................................................557 26.8 Security Settings ...................................................................................................................... 558 26.9 Flash Memory Programming by Self-Writing ........................................................................ 560 26.9.1 Boot swap function.......................................................................................................................563 CHAPTER 27 ON-CHIP DEBUG FUNCTION ( PD78F0376D AND 78F0386D ONLY) ................. 565 27.1 On-Chip Debug ...
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Features Minimum instruction execution time can be changed from high speed (0 MHz operation with high- speed system clock) to ultra low-speed (122 s: @ 32.768 kHz operation with subsystem clock) General-purpose register: 8 bits ROM, ...
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Serial interface: 3 channels • UART (LIN (Local Interconnect Network)-bus supported): 1 channel Note • CSI/UART : 2 • Note Select either of the functions of these alternate-function pins. 10-bit resolution A/D converter: 8 channels ( PD78F037x only) ...
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Ordering Information <R> Flash memory version (Lead-free products) Part Number PD78F0372GC-UBT-A PD78F0373GC-UBT-A PD78F0374GC-UBT-A PD78F0375GC-UBT-A PD78F0376GC-UBT-A PD78F0376DGC-UBT-A PD78F0372GK-8EU-A PD78F0373GK-8EU-A PD78F0374GK-8EU-A PD78F0375GK-8EU-A PD78F0376GK-8EU-A PD78F0376DGK-8EU-A PD78F0382GC-UBT-A PD78F0383GC-UBT-A PD78F0384GC-UBT-A PD78F0385GC-UBT-A PD78F0386GC-UBT-A PD78F0386DGC-UBT-A PD78F0382GK-8EU-A PD78F0383GK-8EU-A PD78F0384GK-8EU-A PD78F0385GK-8EU-A PD78F0386GK-8EU-A PD78F0386DGK-8EU-A Note The PD78F0376D and 78F0386D ...
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Pin Configuration (Top View) (1) PD78F0372, 78F0373, 78F0374, 78F0375, 78F0376, 78F0376D 80-pin plastic LQFP (14 80-pin plastic LQFP (fine pitch) (12 P61/SDA0 P60/SCL0 RESET P124/XT2/EXCLKS P123/XT1 FLMD0 Note P122/X2/EXCLK/OCD0B Note P121/X1/OCD0A REGC CAPH CAPL V ...
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PD78F0382, 78F0383, 78F0384, 78F0385, 78F0386, 78F0386D 80-pin plastic LQFP (14 80-pin plastic LQFP (fine pitch) (12 P124/XT2/EXCLKS P123/XT1 FLMD0 Note P122/X2/EXCLK/OCD0B Note P121/X1/OCD0A REGC CAPH CAPL V LC0 V LC1 V LC2 COM0 COM1 COM2 ...
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Pin Identification Note1 ANI0 to ANI7 : Analog input Note1 AV : Analog reference voltage REF Note1 AV : Analog ground SS CAPH, CAPL: LCD power supply capacitance control COM0 to COM3: Common output EXCLK: External clock input (main system ...
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Series Lineup <R> ROM RAM 128 768 B Note Product with on-chip debug ...
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The list of functions in the 78K0/Lx2 Series is shown below. 78K0/LE2 Part Number PD78F036x Item 64 Pins Flash memory (KB RAM (KB) 0.75 1 Bank (flash memory) Power supply voltage Regulator Minimum instruction execution time High-speed system ...
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Block Diagram <R> TO00/TI010/P01 16-bit TIMER/ EVENT COUNTER 00 TI000/P00 (LINSEL) RxD6/P14 (LINSEL) 16-bit TIMER/EVENT COUNTER 01 TOH0/P15 TOH1/P16 WATCHDOG TIMER 8-bit TIMER/ TI50/TO50/P17 EVENT COUNTER 50 8-bit TIMER/ TI51/TO51/P33 EVENT COUNTER 51 RxD0/P11 SERIAL INTERFACE UART0 TxD0/P10 SERIAL ...
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Outline of Functions ( PD78F037x) Item Internal Flash memory memory (self-programming Note 1 supported) Note 2 Memory bank Note 1 High-speed RAM Note 1 Expansion RAM LCD display RAM Memory space Main system High-speed system clock clock (oscillation ...
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Item PD78F0372 Serial interface • UART supporting LIN-bus: 1 channel • 3-wire serial I/O/UART 2 • bus: LCD controller/driver • Internal voltage boosting, external resistance division, and internal resistance division are switchable. • Segment signal outputs: 26 • ...
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Outline of Functions ( PD78F038x) <R> Item Internal Flash memory memory (self-programming Note 1 supported) Note 2 Memory bank Note 1 High-speed RAM Note 1 Expansion RAM LCD display RAM Memory space Main system High-speed system clock clock (oscillation ...
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Item PD78F0382 Serial interface • UART supporting LIN-bus: 1 channel • 3-wire serial I/O/UART 2 • bus: LCD controller/driver • Internal voltage boosting, external resistance division, and internal resistance division are switchable. • Segment signal outputs: 36 • ...
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Pin Function List There are three types of pin I/O buffer power supplies: AV power supplies and the pins is shown below. Power Supply Note1 AV P20 to P27 REF LV CAPH, CAPL, COM0 to COM3 S25, ...
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Port pins (2/2) Pin Name I/O P70 to P76 I/O Port 7. 7-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P120 I/O Port 12. ...
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Non-port pins (1/2) Pin Name I/O INTP0 Input External interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be INTP1 specified INTP2 INTP3 INTP4 INTP5 SI10 Input Serial data ...
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Non-port pins (2/2) Pin Name I/O CAPH CAPL KR0 to KR6 Input REGC <R> RESET Input EXLVI Input X1 Input X2 EXCLK Input XT1 Input XT2 EXCLKS Input FLMD0 Note OCD0A Input Note OCD1A Note ...
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Description of Pin Functions 2.2.1 P00, P01 (port 0) P00 and P01 function as a 2-bit I/O port. These pins also function as timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P00 ...
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RxD0, RxD6 These are the serial data input pins of the asynchronous serial interface. (e) TxD0, TxD6 These are the serial data output pins of the asynchronous serial interface. (f) TI50 This is the pin for inputting an external ...
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TI51 This is an external count clock input pin to 8-bit timer/event counter 51. (c) TO51 This is a timer output pin. Caution In the PD78F0374, 78F0375, 78F0376, 78F0376D, 78F0384, 78F0385, 78F0386, and 78F0386D, be sure to pull the ...
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P70 to P76 (port 7) P70 to P76 function as a 7-bit I/O port. These pins also function as key interrupt input pins. The following operation modes can be specified in 1-bit units. (1) Port mode P70 to P76 ...
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AV ( PD78F037x only) REF This is the A/D converter reference voltage input pin. When the A/D converter is not used, connect this pin directly to V Note Make the AV pin the same potential as the V REF ...
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V DD This is the positive power supply pin. 2.2. This is the ground potential pin. 2.2.21 FLMD0 This is a pin for setting flash memory programming mode. Connect FLMD0 the normal operation mode. ...
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Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-2 shows the types of pin I/O circuits and the recommended connections of unused pins. See Figure 2-1 for the configuration of the I/O circuit of each type. Pin ...
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Pin Name I/O Circuit Type Note 1 P121/X1 37 Note1 P122/X2/EXCLK Note 1 P123/XT1 Note1 P124/XT2/EXCLKS S0 to S25 17 Note2 S26 to S35 COM0 to COM3 LC0 LC2 CAPH, CAPL RESET 2 FLMD0 38 Note3 ...
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Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 5-AG Pull-up enable V DD Data P-ch Output N-ch disable V SS Input enable Type 5-AH Pull-up enable V DD Data P-ch Output N-ch disable V SS Input enable 42 CHAPTER ...
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Type 18 V LC0 P-ch P-ch V LC1 N-ch P-ch COM data N-ch P-ch V LC2 N-ch N-ch Type Reset Data P-ch Output N-ch disable V SS Input enable V DD Reset Data P-ch Output N-ch disable ...
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Memory Space Products in the 78K0/LF2 can each access memory space. Figures 3-1 to 3-6 show the memory maps. Cautions 1. Regardless of the internal memory capacity, the initial values of the internal memory size switching ...
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Figure 3-1. Memory Map ( PD78F0372, 78F0382 Special function registers (SFR) 256 8 bits General-purpose registers 32 8 bits ...
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Figure 3-2. Memory Map ( PD78F0373, 78F0383 Special function registers (SFR) 256 8 bits General-purpose registers 32 8 bits ...
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Data memory space F ...
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Figure 3-4. Memory Map ( PD78F0375, 78F0385 Special function registers (SFR) 256 8 bits General-purpose registers 32 8 bits ...
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Data memory space F ...
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Special function registers General-purpose bits Internal high-speed RAM ...
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Internal program memory space The internal program memory space stores the program and table data. Normally addressed with the program counter (PC). 78K0/LF2 products incorporate internal ROM (flash memory), as shown below. <R> Part Number PD78F0372, 78F0382 ...
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CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) Option byte area A 5-byte area of 0080H to 0084H and 1080H to 1084H can be ...
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Internal expansion RAM <R> Part Number PD78F0372, 78F0382 PD78F0373, 78F0383 PD78F0374, 78F0384 PD78F0375, 78F0385 PD78F0376, 78F0386, 78F0376D, 78F0386D The internal expansion RAM can also be used as a normal data area similar to the internal high-speed RAM, as well ...
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Figure 3-7. Correspondence Between Data Memory and Addressing ( PD78F0372, 78F0382 Special function registers (SFR) 256 8 bits ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-8. Correspondence Between Data Memory and Addressing ( PD78F0373, 78F0383 Special function registers (SFR) 256 8 bits ...
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Figure 3-9. Correspondence Between Data Memory and Addressing ( PD78F0374, 78F0384 Special function registers (SFR) 256 x 8 bits ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Correspondence Between Data Memory and Addressing ( PD78F0375, 78F0385 Special function registers (SFR) 256 8 bits ...
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Figure 3-11. Correspondence Between Data Memory and Addressing Special function registers (SFR) 256 x 8 bits ...
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Processor Registers The 78K0/LF2 products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and ...
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Zero flag (Z) When the operation result is zero, this flag is set (1 reset (0) in all other cases. (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-15. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEE0H) FEE0H FEE0H SP FEDFH FEDEH SP FEDEH (b) CALL, CALLF, CALLT instructions (when SP = FEE0H) SP FEE0H FEE0H ...
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Figure 3-16. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH (c) RETI, RETB instructions (when SP = FEDDH CHAPTER 3 CPU ARCHITECTURE FEE0H FEE0H FEDFH Register ...
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General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers ( and H). ...
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Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH areas in the CPU, and are allocated to the 00H to 03H areas of LCDCTL ...
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Table 3-7. Special Function Register List (1/4) Address Special Function Register (SFR) Name FF00H Port register 0 FF01H Port register 1 Note FF02H Port register 2 FF03H Port register 3 FF06H Port register 6 FF07H Port register 7 FF08H 10-bit ...
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Table 3-7. Special Function Register List (2/4) Address Special Function Register (SFR) Name FF3CH Pull-up resistor option register 12 FF40H Clock output selection register FF41H 8-bit timer compare register 51 FF43H 8-bit timer mode control register 51 FF48H External interrupt ...
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Table 3-7. Special Function Register List (3/4) Address Special Function Register (SFR) Name FF80H Serial operation mode register 10 FF81H Serial clock selection register 10 FF84H Transmit buffer register 10 FF8CH Timer clock selection register 51 FF99H Watchdog timer enable ...
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Address Special Function Register (SFR) Name FFBEH Low-voltage detection register FFBFH Low-voltage detection level selection register FFE0H Interrupt request flag register 0L FFE1H Interrupt request flag register 0H FFE2H Interrupt request flag register 1L FFE3H Interrupt request flag register 1H ...
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Instruction Address Addressing An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is ...
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Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and ...
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Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits the immediate data of an operation code are transferred to the program counter (PC) and branched. This ...
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Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register that functions as an accumulator (A and AX) among the general-purpose registers ...
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Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes (Rn and RPn operation code. Register addressing is carried ...
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Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. [Operand format] [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code [Illustration ...
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Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function ...
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Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the ...
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Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing ...
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Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and ...
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Based indexed addressing [Function] The register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank ...
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Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation ...
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Memory Bank ( PD78F0376, 78F0376D, 78F0386, AND 78F0386D ONLY) <R> The PD78F0376, 78F0376D, 78F0386, and 78F0386D implement a ROM capacity selecting a memory bank from a memory space of 8000H to BFFFH. The PD78F0376, 78F0376D, ...
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Memory Bank Select Register (BANK) ( PD78F0376, 78F0376D, 78F0386, AND 78F0386D ONLY) <R> The memory bank select register (BANK) is used to select a memory bank to be used. BANK can be set by an 8-bit memory manipulation instruction. ...
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Selecting Memory Bank ( PD78F0376, 78F0376D, 78F0386, AND 78F0386D ONLY) <R> The memory bank selected by the memory bank select register (BANK) is reflected on the bank area and can be addressed. Therefore, to access a memory bank different ...
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Software example (to store a value to be referenced in register A) RAMD DSEG SADDR R_BNKA R_BNKN R_BNKRN ETRC CSEG UNIT ENTRY: MOV R_BNKN,#BANKNUM DATA1 MOVW R_BNKA,#DATA1 CALL !BNKRD : : BNKC CSEG AT ...
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Branching instruction between memory banks Instructions cannot branch directly from one memory bank to another. To branch an instruction from one memory bank to another, branch once to the common area (0000H to 7FFFH), change the setting of the ...
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Software example 1 (to branch from all areas) RAMD DSEG SADDR R_BNKA R_BNKN RSAVEAX ETRC CSEG UNIT ENTRY: MOV R_BNKN,#BANKNUM TEST MOVW R_BNKA,#TEST BR !BNKBR : : BNKC CSEG AT 7000H BNKBR: MOVW RSAVEAX,AX ...
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Subroutine call between memory banks Subroutines cannot be directly called between memory banks. To call a subroutine between memory banks, branch once to the common area (0000H to 7FFFH), specify the memory bank at the calling destination by using ...
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Software example RAMD DSEG SADDR R_BNKA R_BNKN R_BNKRN RSAVEAX ETRC CSEG UNIT ENTRY: MOV R_BNKN,#BANKNUM TEST MOVW R_BNKA,#TEST CALL !BNKCAL : : BNKC CSEG AT 7000H BNKCAL: MOVW RSAVEAX,AX MOV A,R_BNKN XCH ...
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Instruction branch to bank area by interrupt When an interrupt occurs, instructions can branch to the memory bank specified by the BANK register by using the vector table, but it is difficult to identify the BANK register when the ...
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Remark Note the following points to use the memory bank select function efficiently. Allocate a routine that is used often in the common area value that is planned to be referenced is placed in RAM, it can be ...
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Port Functions There are two types of pin I/O buffer power supplies: AV supplies and the pins is shown below. Power Supply AV REF V DD Note PD78F037x only. 78K0/LF2 products are provided with the ports shown in Figure ...
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Pin Name I/O P00 I/O Port 0. 2-bit I/O port. Input/output can be specified in 1-bit units. P01 Use of an on-chip pull-up resistor can be specified by a software setting. P10 I/O Port 1. 8-bit I/O port. P11 Input/output ...
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Port Configuration Ports include the following hardware. Item Control registers Port mode register (PM0 to PM3, PM6. PM7, PM12) Port register (P0 to P3, P6, P7, P12) Pull-up resistor option register (PU0, PU1, PU3, PU7, PU12) A/D port configuration ...
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Port 0 Port 2-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 and P01 ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P01 WR PU PU0 PU01 Alternate function RD WR PORT Output latch (P01 PM0 PM01 Alternate function PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: ...
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Port 1 Port 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P11 and P14 WR PU PU1 PU11, PU14 Alternate function RD WR PORT Output latch (P11, P14 PM1 PM11, PM14 PU1: Pull-up resistor option register 1 PM1: Port mode ...
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Figure 4-6. Block Diagram of P12 and P15 WR PU PU1 PU12, PU15 RD WR PORT Output latch (P12, P15 PM1 PM12, PM15 Alternate function PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P13 WR PU PU1 PU13 RD WR PORT Output latch (P13 PM1 PM13 Alternate function PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal ...
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Figure 4-8. Block Diagram of P16 and P17 WR PU PU1 PU16, PU17 Alternate function RD WR PORT Output latch (P16, P17 PM1 PM16, PM17 Alternate function PU1: Pull-up resistor option register 1 PM1: Port mode register 1 ...
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Port 2 ( PD78F037x only) Port 8-bit I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port mode register 2 (PM2). This port ...
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Port 3 Port 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When used as an input ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of P33 WR PU PU3 PU33 Alternate function RD WR PORT Output latch (P33 PM3 PM33 Alternate function PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: ...
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Port 6 Port 2-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). When the P60 and ...
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Port 7 Port 7-bit I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (PM7). When the P70 to P76 ...
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Port 12 Port 5-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When used as an input ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-15. Block Diagram of P121 to P124 OSCCTL OSCSEL/ OSCSELS RD WR PORT Output latch (P122/P124 PM12 PM122/PM124 OSCCTL OSCSEL/ OSCSELS RD WR PORT Output latch (P121/P123 PM12 PM121/PM123 OSCCTL OSCSEL/ ...
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Registers Controlling Port Function Port functions are controlled by the following four types of registers. Port mode registers (PM0, PM1, PM2 Port registers (P0, P1, P2 Pull-up resistor option registers (PU0, PU1, PU3, PU7, PU12) A/D port configuration register ...
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Port registers (P0, P1, P2 These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level is read ...
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Pull-up resistor option registers (PU0, PU1, PU3, PU7, PU12) These registers specify whether the on-chip pull-up resistors of P00, P01, P10 to P17, P30 to P33, P70 to P76, and P120 are to be used or not. On-chip pull-up ...
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A/D port configuration register (ADPC) ( PD78F037x only) This register switches the P20/ANI0 to P27/ANI7 pins to analog input of A/D converter or digital I/O of port. ADPC can be set by a 1-bit or 8-bit memory manipulation instruction. ...
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Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as ...
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Settings of Port Mode Register and Output Latch When Using Alternate Function When port pins are used as alternate-function pins, set the port mode register and output latch as shown in Table 4-5. Table 4-5. Settings of Port Mode ...
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Notes1. PD78F037x only. 2. The functions of the ANI0/P20 to ANI7/P27 pins are determined according to the settings of A/D port configuration register (ADPC), Analog input channel specification register (ADS), and PM2. Table 4-6. Settings of ANI0/P20 to ANI7/P27 pin ...
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Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three kinds of system clocks and clock oscillators are selectable. (1) Main system clock <1> X1 oscillator This ...
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Internal low-speed oscillation clock (clock for watchdog timer) Internal low-speed oscillator This circuit oscillates a clock of f clock always starts operating. Oscillation can be stopped by using the internal oscillation mode register (RCM) when “internal low-speed oscillator can ...
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Main OSC Clock operation mode select register control register (MOC) (OSCCTL) AMPH EXCLK OSCSEL High-speed system clock oscillator f XH X1/P121 Crystal/ceramic f X oscillation X2/EXCLK/ External input P122 f Internal hgh- EXCLK clock speed oscillator (8 MHz (TYP.)) Subsystem ...
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Remarks clock oscillation frequency Internal high-speed oscillation clock frequency External main system clock frequency EXCLK High-speed system clock oscillation frequency Main ...
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CHAPTER 5 CLOCK GENERATOR Figure 5-2. Format of Clock Operation Mode Select Register (OSCCTL) Address: FF9FH After reset: 00H R/W Symbol <7> <6> OSCCTL EXCLK OSCSEL EXCLKS EXCLK OSCSEL High-speed system clock 0 0 I/O port mode ...
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Processor clock control register (PCC) This register is used to select the CPU clock, the division ratio, and operation mode for subsystem clock. PCC is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PCC ...
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Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution Time CPU Clock (f ) CPU High-Speed System Clock At 10 MHz Operation ...
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Internal oscillation mode register (RCM) This register sets the operation mode of internal oscillator. RCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 80H Figure 5-4. Format of Internal ...
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Main OSC control register (MOC) This register selects the operation mode of the high-speed system clock. This register is used to stop the X1 oscillator or to disable an external clock input from the EXCLK pin when the CPU ...
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Main clock mode register (MCM) This register selects the main system clock supplied to CPU clock and clock supplied to peripheral hardware clock. MCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets ...
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Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. When X1 clock oscillation starts with the internal high-speed oscillation clock or subsystem clock used ...
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Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation waits for ...
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System Clock Oscillator 5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator ( MHz) connected to the X1 and X2 pins. Figure 5-9 shows an example of the external circuit of the ...
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Cautions 1. When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the broken lines in the Figures 5-9 and 5-10 to avoid an adverse effect from wiring capacitance. • Keep the wiring length ...
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Figure 5-11. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (e) Signals are fetched Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, ...
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When subsystem clock is not used not necessary to use the subsystem clock for low power consumption operations not using the subsystem clock as an I/O port, set the XT1 and XT2 pins to ...
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Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode (see Figure 5-1). Main system clock f XP High-speed system clock clock f X ...
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Figure 5-12. Clock Generator Operation When Power Supply Voltage Is Turned On (When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0)) Power supply 1.8 V voltage ( 1.59 V (TYP.) 0.5 V/ms (MAX ...
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Remark While the microcontroller is operating, a clock that is not used as the CPU clock can be stopped via software settings. The internal high-speed oscillation clock and high-speed system clock can be stopped by executing the STOP instruction (see ...
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Remark While the microcontroller is operating, a clock that is not used as the CPU clock can be stopped via software settings. The internal high-speed oscillation clock and high-speed system clock can be stopped by executing the STOP instruction (see ...
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Waiting for the stabilization of the oscillation of X1 clock Check the OSTC register and wait for the necessary time. During the wait time, other software processing can be executed with the internal high-speed oscillation clock. Cautions 1. Do ...
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Setting the high-speed system clock as the main system clock (MCM register) When XSEL and MCM0 are set to 1, the high-speed system clock is supplied as the main system clock and peripheral hardware clock. XSEL MCM0 1 1 ...
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To stop X1 oscillation (disabling external clock input) by setting MSTOP to 1 <1> Confirming the CPU clock status (PCC and MCM registers) Confirm with CLS and MCS that the CPU is operating on a clock other than the ...
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Example of setting procedure when using internal high-speed oscillation clock as CPU clock, and internal high-speed oscillation clock or high-speed system clock as peripheral hardware clock <1> Restarting oscillation of the internal high-speed oscillation clock (See 5.6.2 (1) Example ...
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To stop internal high-speed oscillation clock by setting RSTOP to 1 <1> Confirming the CPU clock status (PCC and MCM registers) Confirm with CLS and MCS that the CPU is operating on a clock other than the internal high-speed ...
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Example of setting procedure when using the external subsystem clock <1> Setting XT1 and XT2 pins, selecting XT1 clock/external clock and controlling oscillation (PCC and OSCCTL registers) When XTSTART is cleared to 0 and EXCLKS and OSCSELS are set ...
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Example of controlling internal low-speed oscillation clock The internal low-speed oscillation clock cannot be used as the CPU clock. Only the following peripheral hardware can operate with this clock. Watchdog timer 8-bit timer H1 ( selected as ...
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CPU clock status transition diagram Figure 5-14 shows the CPU clock status transition diagram of this product. Figure 5-14. CPU Clock Status Transition Diagram (When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0)) Internal low-speed oscillation: ...
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Table 5-5 shows transition of the CPU clock and examples of setting the SFR registers. Table 5-5. CPU Clock Transition and SFR Register Setting Examples (1/4) (1) CPU operating with internal high-speed oscillation clock (B) after reset release (A) Status ...
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Table 5-5. CPU Clock Transition and SFR Register Setting Examples (2/4) (4) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (B) (C) ...
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Table 5-5. CPU Clock Transition and SFR Register Setting Examples (3/4) (6) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (C) (B) ...
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Table 5-5. CPU Clock Transition and SFR Register Setting Examples (4/4) (9) CPU clock changing from subsystem clock (D) to high-speed system clock (C) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (D) (C) (X1 clock: ...
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Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. CPU Clock Before Change After Change Internal high- X1 clock Stabilization of ...
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Time required for switchover of CPU clock and main system clock By setting bits (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC), the CPU clock can be switched (between the ...
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Table 5-8. Maximum Time Required for Main System Clock Switchover Set Value Before Switchover MCM0 0 1 Caution When switching the internal high-speed oscillation clock to the high-speed system clock, bit 2 (XSEL) of MCM must be set to 1 ...
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Peripheral hardware and source clocks The following lists peripheral hardware and source clocks incorporated in the 78K0/LF2. Table 5-10. Peripheral Hardware and Source Clocks Source Clock Peripheral Hardware Clock Peripheral Hardware (f PRS 16-bit timer event counter ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 The PD78F0372, 78F0373, 78F0382, and 78F0383 incorporate 16-bit timer/event counter 00, and the PD78F0374, 78F0375, 78F0376, 78F0376D, 78F0384, 78F0385, 78F0386, and 78F0386D incorporate 16-bit timer/event counter 00 and 16-bit timer 01. 6.1 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.2 Configuration of 16-Bit Timer/Event Counters 00 and 01 16-bit timer/event counters 00 and 01 include the following hardware. Table 6-1. Configuration of 16-Bit Timer/Event Counters 00 and 01 Item Timer counter ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-2. Block Diagram of 16-Bit Timer/Event Counter 01 ( PD78F0374, 78F0375, 78F0376, 78F0376D, 78F0384, 78F0385, 78F0386, and 78F0386D Only) f PRS PRS PRS 2 PRM011 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (1) 16-bit timer counter 0n (TM0n) TM0n is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the input clock. Figure 6-3. ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 When CR000 is used as a capture register It is possible to select the valid edge of the TI000 pin or the TI010 pin as the capture trigger. The TI000 or TI010 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (3) 16-bit timer capture/compare register 010 (CR010) CR010 is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is used as a capture ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (4) 16-bit timer capture/compare register 001 (CR001) CR001 is a 16-bit compare register. CR001 can be set by a 16-bit memory manipulation instruction. Reset signal generation sets this register to 0000H. Note ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.3 Registers Controlling 16-Bit Timer/Event Counters 00 and 01 The following six registers are used to control 16-bit timer/event counters 00 and 01. 16-bit timer mode control register 0n (TMC0n) Capture/compare control ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-8. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address FFBAH After reset: 00H R/W Symbol TMC00 TMC003 TMC003 TMC002 TMC001 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-9. Format of 16-Bit Timer Mode Control Register 01 (TMC01) Address FFB6H After reset: 00H R/W Symbol TMC01 TMC013 TMC013 TMC012 Operating ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (2) Capture/compare control register 00 (CRC00) This register controls the operation of the 16-bit timer capture/compare registers (CR000, CR010). CRC00 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-11. Format of 16-Bit Timer Output Control Register 00 (TOC00) Address: FFBDH After reset: 00H Symbol 7 <6> TOC00 0 OSPT00 OSPT00 0 No one-shot pulse output trigger 1 One-shot pulse ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (4) Prescaler mode register 0n (PRM0n) This register is used to set the 16-bit timer counter 0n (TM0n) count clock and TI000 and TI010 pin input valid edges. PRM0n can be set ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Cautions 1. Always set data to PRM00 after stopping the timer operation the valid edge of the TI000 pin set for the count clock, do not set ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (5) Port mode register 0 (PM0) This register sets port 0 input/output in 1-bit units. When using the P01/TO00/TI010 pin for timer output, set PM01 and the output latches of P01 to ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.4 Operation of 16-Bit Timer/Event Counters 00 and 01 6.4.1 Interval timer operation Setting 16-bit timer mode control register 0n (TMC0n) and capture/compare control register 00 (CRC00) as shown in Figure 6-15 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-15. Control Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 0n (TMC0n TMC0n3 TMC0n (b) Capture/compare control register 00 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-16. Interval Timer Configuration Diagram Note PRS, PRS 2 Note 1 4 Note PRS PRS 8 Note 1 6 Note 2 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.4.2 PPG output operations (timer 00 only) Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown in Figure 6-18 allows operation as PPG (Programmable Pulse ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-18. Control Register Settings for PPG Output Operation (a) 16-bit timer mode control register 00 (TMC00 TMC00 (b) Capture/compare control register 00 (CRC00) ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-19. Configuration Diagram of PPG Output f PRS PRS PRS Noise TI000/P00 eliminator f PRS Figure 6-20. PPG Output Operation Timing Count clock TM00 count ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.4.3 Pulse width measurement operations (timer 00 only possible to measure the pulse width of the signals input to the TI000 pin and TI010 pin using 16-bit timer counter 00 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (1) Pulse width measurement with free-running counter and one capture register When 16-bit timer counter 00 (TM00) is operated in free-running mode, and the edge specified by prescaler mode register 00 (PRM00) ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-23. Configuration Diagram for Pulse Width Measurement with Free-Running Counter f PRS PRS PRS TI000 Figure 6-24. Timing of Pulse Width Measurement Operation with Free-Running ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (2) Measurement of two pulse widths with free-running counter When 16-bit timer counter 00 (TM00) is operated in free-running mode possible to simultaneously measure the pulse widths of the two ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-26. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) t Count clock 0000H 0001H TM00 count value TI000 pin input CR010 capture value INTTM010 TI010 pin ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer counter 00 (TM00) is operated in free-running mode possible to measure the pulse width of the ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-28. Timing of Pulse Width Measurement Operation with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) t Count clock TM00 count value 0000H 0001H TI000 pin input CR010 capture ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-29. Control Register Settings for Pulse Width Measurement by Means of Restart (a) 16-bit timer mode control register 00 (TMC00 TMC00 (b) Capture/compare ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.4.4 External event counter operation (timer 00 only) Setting The basic operation setting procedure is as follows. <1> Set the CRC00 register (see Figure 6-31 for the set value). <2> Set the ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-31. Control Register Settings in External Event Counter Mode (with Rising Edge Specified) (a) 16-bit timer mode control register 00 (TMC00 TMC003 TMC00 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-32. Configuration Diagram of External Event Counter Noise eliminator f PRS Valid edge of TI000 pin Note OVF00 is set to 1 only when CR000 is set to FFFFH. Figure 6-33. ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.4.5 Square-wave output operation (timer 00 only) Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM00 register. <2> Set the CRC00 register (see ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-34. Control Register Settings in Square-Wave Output Mode (2/2) (c) 16-bit timer output control register 00 (TOC00) 7 OSPT00 OSPE00 TOC004 LVS00 TOC00 ES101 ES100 ES001 ES000 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.4.6 One-shot pulse output operation (timer 00 only) 16-bit timer/event counter 00 can output a one-shot pulse in synchronization with a software trigger or an external trigger (TI000 pin input). Setting The ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-36. Control Register Settings for One-Shot Pulse Output with Software Trigger (a) 16-bit timer mode control register 00 (TMC00 TMC00 (b) Capture/compare control register 00 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-37. Timing of One-Shot Pulse Output Operation with Software Trigger Set TMC00 to 04H (TM00 count starts) Count clock TM00 count 0000H 0001H CR010 set value N CR000 set value M ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-38. Control Register Settings for One-Shot Pulse Output with External Trigger (a) 16-bit timer mode control register 00 (TMC00 TMC00 (b) Capture/compare control register 00 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-39. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) When TMC00 is set to 08H (TM00 count starts) t Count clock TM00 count value 0000H 0001H ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.5 Cautions for 16-Bit Timer/Event Counters 00 and 01 (1) Timer start errors An error one clock may occur in the time required for a match signal to be ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (6) Operation of OVF0n flag <1> The OVF0n flag is also set the following case. When of the following modes: the mode in which clear & start occurs on ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (8) Timer operation <1> Even if 16-bit timer counter 00 (TM00) is read, the value is not captured by 16-bit timer capture/compare register 010 (CR010). <2> Regardless of the CPU’s operation mode, ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.1 Functions of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 have the following functions. Interval timer External event counter Square-wave output PWM output 7.2 Configuration of 8-Bit ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-1. Block Diagram of 8-Bit Timer/Event Counter 50 8-bit timer compare register 50 (CR50) TI50/TO50/P17 Match f PRS f /2 PRS PRS 8-bit timer PRS ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (1) 8-bit timer counter 5n (TM5n) TM5n is an 8-bit register that counts the count pulses and is read-only. The counter is incremented in synchronization with the rising edge of the count ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 The following four registers are used to control 8-bit timer/event counters 50 and 51. Timer clock selection register 5n (TCL5n) 8-bit timer mode ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-6. Format of Timer Clock Selection Register 51 (TCL51) Address: FF8CH After reset: 00H Symbol 7 6 TCL51 0 0 TCL512 TCL511 ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer mode control register 5n (TMC5n) TMC5n is a register that performs the following five types of settings. <1> 8-bit timer counter 5n (TM5n) count operation control <2> 8-bit timer ...