UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 15

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 13 MULTIPLIER .................................................................................................................. 546
CHAPTER 14 DMA CONTROLLER..................................................................................................... 549
CHAPTER 15 INTERRUPT FUNCTIONS ............................................................................................ 576
12.6 Timing Charts ........................................................................................................................... 539
13.1 Functions of Multiplier............................................................................................................. 546
13.2 Configuration of Multiplier ...................................................................................................... 547
13.3 Operation of Multiplier............................................................................................................. 548
14.1 Functions of DMA Controller .................................................................................................. 549
14.2 Configuration of DMA Controller............................................................................................ 550
14.3 Registers Controlling DMA Controller ................................................................................... 553
14.4 Operation of DMA Controller .................................................................................................. 557
14.5 Example of Setting of DMA Controller................................................................................... 560
14.6 Cautions on Using DMA Controller ........................................................................................ 573
15.1 Interrupt Function Types......................................................................................................... 576
15.2 Interrupt Sources and Configuration ..................................................................................... 576
15.3 Registers Controlling Interrupt Functions ............................................................................ 581
15.4 Interrupt Servicing Operations ............................................................................................... 591
12.5.3 Transfer direction specification .....................................................................................................493
12.5.4 Transfer clock setting method .......................................................................................................494
12.5.5 Acknowledge (ACK) ......................................................................................................................495
12.5.6 Stop condition ...............................................................................................................................497
12.5.7 Wait...............................................................................................................................................498
12.5.8 Canceling wait...............................................................................................................................500
12.5.9 Interrupt request (INTIIC0) generation timing and wait control......................................................501
12.5.10 Address match detection method................................................................................................502
12.5.11 Error detection ............................................................................................................................502
12.5.12 Extension code ...........................................................................................................................502
12.5.13 Arbitration....................................................................................................................................503
12.5.14 Wakeup function .........................................................................................................................504
12.5.15 Communication reservation ........................................................................................................505
12.5.16 Cautions......................................................................................................................................509
12.5.17 Communication operations .........................................................................................................510
12.5.18 Timing of I
14.4.1 Operation procedure .....................................................................................................................557
14.4.2 Transfer mode...............................................................................................................................559
14.4.3 Termination of DMA transfer .........................................................................................................559
14.5.1 CSI consecutive transmission .......................................................................................................560
14.5.2 CSI master reception ....................................................................................................................562
14.5.3 CSI transmission/reception ...........................................................................................................564
14.5.4 Consecutive capturing of A/D conversion results..........................................................................566
14.5.5 UART consecutive reception + ACK transmission ........................................................................568
14.5.6 Holding DMA transfer pending by DWAITn...................................................................................570
14.5.7 Forced termination by software.....................................................................................................571
15.4.1 Maskable interrupt acknowledgment.............................................................................................591
2
C interrupt request (INTIIC0) occurrence ..................................................................518
User’s Manual U17854EJ9V0UD
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