UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 167

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Example of setting procedure when using the external main system clock
(3) Example of setting procedure when using high-speed system clock as CPU/peripheral hardware clock
<1> Setting P121/X1 and P122/X2/EXCLK pins (CMC register)
<2> Controlling external main system clock input (CSC register)
Cautions 1. The CMC register can be written only once after reset release, by an 8-bit memory
<1> Setting high-speed system clock oscillation
<2> Setting the high-speed system clock as the source clock of the CPU/peripheral hardware clock and
Remarks 1. ×: don’t care
When MSTOP is cleared to 0, the input of the external main system clock is enabled.
(See 5.6.1 (1) Example of setting procedure when oscillating the X1 clock and (2) Example of
setting procedure when using the external main system clock.)
Note The setting of <1> is not necessary when high-speed system clock is already operating.
setting the division ratio of the set clock (CKC register)
Note Setting is prohibited when f
EXCLK
MCM0
2. Set the external main system clock after the supply voltage has reached the operable
1
1
manipulation instruction.
Therefore, it is necessary to also set the value of the OSCSELS bits at the same time. For
OSCSELS bits, see 5.6.3 Example of controlling subsystem clock.
voltage of the clock to be used (see CHAPTER 27
(STANDARD PRODUCTS) and CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A) GRADE
PRODUCTS)).
2. For setting of the P123/XT1 and P124/XT2 pins, see 5.6.3 (1)
OSCSEL
procedure when oscillating the subsystem clock.
MDIV2
1
0
0
0
0
1
1
MDIV1
0
0
CHAPTER 5 CLOCK GENERATOR
0
0
1
1
0
0
User’s Manual U17854EJ9V0UD
MX
OSCSELS
< 4 MHz.
MDIV0
0/1
0
1
0
1
0
1
Note
f
f
f
f
f
f
MX
MX
MX
MX
MX
MX
/2
/2
/2
/2
/2
0
0
2
3
4
5 Note
Selection of CPU/Peripheral
Hardware Clock (f
0
0
ELECTRICAL SPECIFICATIONS
0
0
CLK
)
Example of setting
AMPH
×
165