UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 174

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UPD78F1146AGB-GAH-AX

Manufacturer Part Number
UPD78F1146AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1146AGB-GAH-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1146AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
5.6.5 CPU clock status transition diagram
Remark
172
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input:
Oscillatable
XT1 oscillation: Operating
Figure 5-15 shows the CPU clock status transition diagram of this product.
Internal high-speed oscillation:
Oscillatable
X1 oscillation/EXCLK input:
Oscillatable
XT1 oscillation: Operating
If the low-power-supply detector (LVI) is set to ON by default by the option bytes, the reset will not be
released until the power supply voltage (V
After the reset operation, the status will shift to (B) in the above figure.
Internal high-speed oscillation:
Oscillatable
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation: Operating
Internal high-speed oscillation:
Oscillatable
X1 oscillation/EXCLK input:
Oscillatable
XT1 oscillation: Operating
(D)
(G)
XT1 oscillation
Operating with
XT1 oscillation
→ HALT
CPU:
CPU:
Internal high-speed oscillation:
Operating
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation: Selectable by CPU
Figure 5-15. CPU Clock Status Transition Diagram
(G)
(D)
XT1 oscillation
Operating with
XT1 oscillation
CHAPTER 5 CLOCK GENERATOR
CPU:
CPU:
HALT
User’s Manual U17854EJ9V0UD
(A)
(B)
(C)
DD
Reset release
with X1 oscillation
with internal high-
speed oscillation
CPU: Operating
CPU: Operating
or EXCLK input
Power ON
) exceeds 2.07 V±0.2 V.
(F)
oscillation/EXCLK
input → HALT
CPU: X1
Internal high-speed
oscillation:
Selectable by CPU
X1 oscillation/EXCLK
input: Operating
XT1 oscillation:
Selectable by CPU
Internal high-speed oscillation:
Oscillatable
X1 oscillation/EXCLK input:
Operating
XT1 oscillation: Oscillatable
Internal high-speed oscillation: Woken up
X1 oscillation/EXCLK input:
Stops (input port mode)
XT1 oscillation: Stops (input port mode)
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input:
Stops (input port mode)
XT1 oscillation: Stops (input port mode)
(I)
oscillation/EXCLK
V
V
input → STOP
V
DD
DD
DD
CPU: X1
< 1.59 V±0.09 V
≥ 1.59 V±0.09 V
≥ 1.8 V
(H)
(E)
CPU: Internal high-
CPU: Internal high-
speed oscillation
speed oscillation
Internal high-speed oscillation:
Stops
X1 oscillation/EXCLK input:
Stops
XT1 oscillation: Oscillatable
→ HALT
→ STOP
Internal high-speed oscillation:
Operating
X1 oscillation/EXCLK input:
Oscillatable
XT1 oscillation: Oscillatable
Internal high-speed oscillation:
Stops
X1 oscillation/EXCLK input:
Stops
XT1 oscillation: Oscillatable

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