UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 198

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

196
Address: F01B2H, F01B3H
(6) Timer channel start register 0 (TS0)
Symbol
TS0
TS0 is a trigger register that is used to clear a timer counter (TCR0n) and start the counting operation of each
channel.
When a bit (TS0n) of this register is set to 1, the corresponding bit (TE0n) of timer channel enable status
register 0 (TE0) is set to 1. TS0n is a trigger bit and cleared immediately when TE0n = 1.
TS0 can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of TS0 can be set with a 1-bit or 8-bit memory manipulation instruction with TS0L.
Reset signal generation clears this register to 0000H.
Caution Be sure to clear bits 15 to 8 to “0”.
Remarks 1. When the TS0 register is read, 0 is always read.
Table 6-4. Operations from Count Operation Enabled State to TCR0n Count Start (1/2)
TS0n
• Interval timer mode
• Event counter mode
• Capture mode
15
0
1
0
2. n = 0 to 7
Timer operation mode
No trigger operation
TE0n is set to 1 and the count operation becomes enabled.
The TCR0n count operation start in the count operation enabled state varies depending on each operation
mode (see Table 6-4).
14
0
Figure 6-9. Format of Timer Channel Start Register 0 (TS0)
After reset: 0000H
13
0
12
0
11
0
CHAPTER 6 TIMER ARRAY UNIT
No operation is carried out from start trigger detection (TS0n=1) until count clock
generation.
The first count clock loads the value of TDR0n to TCR0n and the subsequent
count clock performs count down operation (see 6.3 (6) (a) Start timing in
interval timer mode).
Writing 1 to TS0n bit loads the value of TDR0n to TCR0n.
The subsequent count clock performs count down operation.
The external trigger detection selected by STS0n2 to STS0n0 bits in the TMR0n
register does not start count operation (see 6.3 (6) (b) Start timing in event
counter mode).
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads 0000H to TCR0n and the subsequent count clock
performs count up operation (see 6.3 (6) (c) Start timing in capture mode).
User’s Manual U17854EJ9V0UD
R/W
10
0
Operation enable (start) trigger of channel n
9
0
8
0
TS07 TS06 TS05 TS04 TS03 TS02 TS01 TS00
Operation when TS0n = 1 is set
7
6
5
4
3
2
1
0