UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 208

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
<R>
206
Address: FFF3CH
(13) Input switch control register (ISC)
Symbol
(14) Noise filter enable register 1 (NFEN1)
ISC
Remark Since the 78K0R/KE3 does not have the timer input pin on channel 7, normally the timer input on
ISC is used to implement LIN-bus communication operation with channel 7 in association with serial array unit
1.
When bit 1 of this register is set to 1, the input signal of the serial data input pin (RxD3) is selected as a timer
input signal.
ISC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Caution Be sure to clear bits 7 to 2 to “0”.
NFEN1 is used to set whether the noise filter can be used for the timer input signal to each channel.
Enable the noise filter by setting the corresponding bits to 1 on the pins in need of noise removal.
When the noise filter is ON, match detection and synchronization of the 2 clocks is performed with the
CPU/peripheral hardware clock (f
the CPU/peripheral hardware clock (f
NFEN1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
ISC1
ISC0
channel 7 cannot be used. When the LIN-bus communication function is used, select the input
signal of the RxD3 pin by setting ISC1 to 1 and setting TIS07 (bit 7 of the timer input select register
0 (TIS0)) to 0.
0
1
0
1
7
0
After reset: 00H
Not uses the input signal (normal operation).
Input signal of R
(to measure the pulse widths of the sync break field and sync field).
Uses the input signal of the INTP0 pin as an external interrupt (normal operation).
Uses the input signal of the R
Figure 6-21. Format of Input Switch Control Register (ISC)
6
0
R/W
X
CHAPTER 6 TIMER ARRAY UNIT
D3 pin is used as timer input
CLK
5
0
). When the noise filter is OFF, only synchronization is performed with
CLK
User’s Manual U17854EJ9V0UD
).
Switching channel 7 input of timer array unit
X
Switching external interrupt (INTP0) input
D3 pin as an external interrupt (wakeup signal detection).
4
0
3
0
0
2
ISC1
1
ISC0
0