UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 215

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Master channel
Slave channel
(b) Set/reset timing
Remarks 1. to_reset: TO0n pin reset/toggle signal
To realize 0%/100% output at PWM output, the TO0n pin/TO0n set timing at master channel timer interrupt
(INTTM0n) generation is delayed by 1 count clock by the slave channel.
If the set condition and reset condition are generated at the same time, a higher priority is given to the
latter.
Figure 6-29 shows the set/reset operating statuses where the master/slave channels are set as follows.
Master channel: TOE0n = 1, TOM0n = 0, TOL0n = 0
Slave channel:
(Internal signal)
(Internal signal)
(Internal signal)
2. n = 0 to 6 (where n = 0, 2, or 4 for master channel)
3. p = n+1, n+2, n+3 ... (where p ≤ 6)
Count clock
to_set:
TO0n pin/
TO0p pin/
INTTM0n
INTTM0p
to_reset
to_reset
to_set
TO0n
TO0p
f
CLK
TOE0p = 1, TOM0p = 1, TOL0p = 0
TO0n pin set signal
Figure 6-29. Set/Reset Timing Operating Statuses
Delays to_reset by 1 count
clock with slave channel
CHAPTER 6 TIMER ARRAY UNIT
Toggle
User’s Manual U17854EJ9V0UD
Set
Reset
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