UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 219

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UPD78F1146AGB-GAH-AX

Manufacturer Part Number
UPD78F1146AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1146AGB-GAH-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1146AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
6.6 Basic Function of Timer Array Unit
6.6.1 Overview of single-operation function and combination-operation function
operate independently, and a combination-operation function that uses two or more channels in combination.
periods) and a slave channel (timer that operates in accordance with the master channel), and several rules must be
observed when using this function.
6.6.2 Basic rules of combination-operation function
The timer array unit consists of several channels and has a single-operation function that allows each channel to
The single-operation function can be used for any channel, regardless of the operation mode of the other channels.
The combination-operation function is realized by combining a master channel (reference timer that mainly counts
The basic rules of using the combination-operation function are as follows.
(1) Only an even channel (channel 0, 2, 4, etc.) can be set as a master channel.
(2) Any channel, except channel 0, can be set as a slave channel.
(3) The slave channel must be lower than the master channel.
(4) Two or more slave channels can be set for one master channel.
(5) When two or more master channels are to be used, slave channels with a master channel between them may
(6) The operating clock for a slave channel in combination with a master channel must be the same as that of the
(7) A master channel can transmit INTTM0n (interrupt), start software trigger, and count clock to the lower
(8) A slave channel can use the INTTM0n (interrupt), start software trigger, and count clock of the master channel,
(9) A master channel cannot use the INTTM0n (interrupt), start software trigger, and count clock from the other
(10) To simultaneously start channels that operate in combination, the TS0n bit of the channels in combination
(11) During a counting operation, the TS0n bit of all channels that operate in combination or only the master
(12) To stop the channels in combination simultaneously, the TT0n bit of the channels in combination must be set
Remark
Example: If channel 2 is set as a master channel, channel 3 or those that follow (channels 3, 4, 5, etc.) can
not be set.
Example: If channels 0 and 4 are set as master channels, channels 1 to 3 can be set as the slave channels
master channel. The CKS bit (bit 15 of the TMR0n register) of the slave channel that operates in combination
with the master channel must be the same value as that of the master channel.
channels.
but it cannot transmit its own INTTM0n (interrupt), start software trigger, and count clock to the lower channel.
master channel.
must be set at the same time.
channel can be set. TS0n of only a slave channel cannot be set.
at the same time.
n = 0 to 7
be set as a slave channel.
of master channel 0. Channels 5 to 7 cannot be set as the slave channels of master channel 0.
CHAPTER 6 TIMER ARRAY UNIT
User’s Manual U17854EJ9V0UD
217

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