UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 224

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UPD78F1146AGB-GAH-AX

Manufacturer Part Number
UPD78F1146AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1146AGB-GAH-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1146AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
222
TMR0n
Figure 6-37. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output
TPS0
(2) When f
TIS0
TO0
(a) Timer mode register 0n (TMR0n)
(b) Timer clock select register 0 (TPS0)
(c) Timer input select register 0 (TIS0)
(d) Timer output register 0 (TO0)
Remarks 1. n = 0 to 7, m = 0, 1, k = 0 to 6
PRS0m3 to PRS0m0
Bits 7 to 4, 3 to 0
CKS0n
TIS0n
TO0k
Bit n
Bit k
1/0
1/0
15
1
SUB
0000
Operation clock selection
2. f
/4 is selected as count clock
14
0: Selects CK00 as operation clock of channel n.
1: Selects CK01 as operation clock of channel n.
f
0
CLK
SUB
(no division) is selected as selected operation clock by TPS0 register.
1: Selects subsystem clock divided by four (f
0: Outputs 0 from TO0k.
1: Outputs 1 from TO0k.
13
: Subsystem clock oscillation frequency
0
0000B: Selects f
m = 0 (bits 0 to 3) when CK00 is selected and m = 1 (bits 4 to 7) when CK01 is selected
CCS0n
12
1
Count clock selection
TER0n
MAS
11
1: Selects subsystem clock divided by four (f
0
CLK
CHAPTER 6 TIMER ARRAY UNIT
Slave/master selection
STS0n2
10
0: Cleared to 0 when single-operation function is selected.
(no division) as operation clock selected by CKS0n of TMR0n register.
0
User’s Manual U17854EJ9V0UD
STS0n1
9
0
Start trigger selection
STS0n0
(2/3)
000B: Selects only software start.
8
0
CIS0n1
1/0
SUB
7
/4).
CIS0n0
1/0
6
f
SUB
00B: Detects falling edge (counts on f
01B: Detects rising edge (counts on f
10B: Detects both edges (counts on f
11B: Setting prohibited
Operation mode of channel n
/4 edge selection
000B: Interval timer
0
5
Setting of operation when counting is started
SUB
0: Neither generates INTTM0n nor inverts
1: Generates INTTM0n and inverts timer
/4).
timer output when counting is started.
output when counting is started.
4
0
MD0n3
3
0
MD0n2
2
0
MD0n1
1
0
SUB
SUB/
MD0n0
SUB
1/0
0
/4 cycles).
/4 cycles).
2 cycles).

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