UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 233

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

TAU
default
setting
Channel
default
setting
Operation
start
During
operation
Operation
stop
TAU stop
Sets the TAU0EN bit of the PER0 register to 1.
Sets the TPS0 register.
Sets the TMR00 register (determines operation mode of
channel).
Sets interval (period) value to the TDR00 register.
Clears the TOM00 bit of the TOM0 register to 0 (toggle
mode).
Clears the TOL00 bit to 0.
Sets the TO00 bit and determines default level of the
TO00 output.
Sets TOE00 to 1 and enables operation of TO00.
Clears the port register and port mode register to 0.
Sets the TOE00 to 1 (only when operation is resumed).
Sets the TS00 bit to 1.
Set value of the TDR00 register can be changed.
The TCR00 register can always be read.
The TSR00 register is not used.
Set values of TO0 and TOE0 registers can be changed.
Set values of the TMR00 register, TOM00, and TOL00
bits cannot be changed.
The TT00 bit is set to 1.
TOE00 is cleared to 0 and value is set to the TO00 bit.
To hold the TO00 pin output level
When holding the TO00 pin output level is not
necessary
The TAU0EN bit of the PER0 register is cleared to 0.
Determines clock frequencies of CK00 and CK01.
The TS00 bit automatically returns to 0 because it is a
trigger bit.
The TT00 bit automatically returns to 0 because it is a
trigger bit.
Clears TO00 bit to 0 after the value to
be held is set to the port register.
Switches the port mode register to input mode.
Figure 6-46. Operation Procedure When Frequency Divider Function Is Used
Software Operation
CHAPTER 6 TIMER ARRAY UNIT
User’s Manual U17854EJ9V0UD
Channel stops operating.
(Clock is supplied and some power is consumed.)
Counter (TCR00) counts down. When count value reaches
0000H, the value of TDR00 is loaded to TCR00 again, and
the count operation is continued. By detecting TCR00 =
0000H, INTTM00 is generated and TO00 performs toggle
operation.
After that, the above operation is repeated.
The TO00 pin outputs the TO00 set level.
The TO00 pin output level is held by port function.
The TO00 pin output level goes into Hi-Z output state.
Power-off status
Power-on status. Each channel stops operating.
The TO00 pin goes into Hi-Z output state.
The TO00 default setting level is output when the port mode
register is in output mode and the port register is 0.
TO00 does not change because channel stops operating.
The TO00 pin outputs the TO00 set level.
TE00 = 1, and count operation starts.
TE00 = 0, and count operation stops.
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
(Clock supply is started and writing to each register is
enabled.)
Value of TDR00 is loaded to TCR00 at the count clock
input. INTTM00 is generated and TO00 performs toggle
operation if the MD000 bit of the TMR00 register is 1.
TCR00 holds count value and stops.
The TO00 output is not initialized but holds current status.
All circuits are initialized and SFR of each channel is also
initialized.
(The TO00 bit is cleared to 0 and the TO00 pin is set to
port mode).
Hardware Status
231