UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 234

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.7.4 Operation as input pulse interval measurement
clock.
same time, the counter (TCR0n) is cleared to 0000H, and the INTTM0n is output. If the counter overflows at this time,
the OVF bit of the TSR0n register is set to 1. If the counter does not overflow, the OVF bit is cleared. After that, the
above operation is repeated.
depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the
captured value can be checked.
bit of the TSR0n register is set to 1. However, the OVF bit is configured as a cumulative flag, the correct interval
value cannot be measured if an overflow occurs more than twice.
capture trigger.
232
The count value can be captured at the TI0k valid edge and the interval of the pulse input to TI0k can be measured.
The pulse interval can be calculated by the following expression.
TCR0n operates as an up counter in the capture mode.
When the channel start trigger (TS0n) is set to 1, TCR0n counts up from 0000H in synchronization with the count
When the TI0k pin input valid edge is detected, the count value is transferred (captured) to TDR0n and, at the
As soon as the count value has been captured to the TDR0n register, the OVF bit of the TSR0n register is updated
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF
Set STS0n2 to STS0n0 of the TMR0n register to 001B to use the valid edges of TI0k as a start trigger and a
When TE0n = 1, instead of the TI0k pin input, a software operation (TS0n = 1) can be used as a capture trigger.
Operation clock
Remark
TI0k input pulse interval = Period of count clock × ((10000H × TSR0n: OVF) + (Capture value of TDR0n + 1))
Caution The TI0k pin input is sampled using the operating clock selected with the CKS0n bit of the
TI0k pin
Figure 6-47. Block Diagram of Operation as Input Pulse Interval Measurement
TMR0n register, so an error equal to the number of operating clocks occurs.
n = 0 to 7, k = 0 to 6
CK01
CK00
TS0n
detection
Edge
CHAPTER 6 TIMER ARRAY UNIT
User’s Manual U17854EJ9V0UD
Timer counter
Data register
(TCR0n)
(TDR0n)
controller
Interrupt
Interrupt signal
(INTTM0n)