UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 238

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.7.5 Operation as input signal high-/low-level width measurement
(high-level width/low-level width) of TI0k can be measured. The signal width of TI0k can be calculated by the
following expression.
is set.
counter counts up in synchronization with the count clock. When the valid capture edge (falling edge of TI0k when the
high-level width is to be measured) is detected later, the count value is transferred to TDR0n and, at the same time,
INTTM0n is output. If the counter overflows at this time, the OVF bit of the TSR0n register is set to 1. If the counter
does not overflow, the OVF bit is cleared. TCR0n stops at the value “value transferred to TDR0n + 1”, and the TI0k
pin start edge detection wait status is set. After that, the above operation is repeated.
depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the
captured value can be checked.
bit of the TSR0n register is set to 1. However, the OVF bit is configured as an integral flag, and the correct interval
value cannot be measured if an overflow occurs more than once.
CIS0n1 and CIS0n0 bits of the TMR0n register.
is 1.
236
By starting counting at one edge of TI0k and capturing the number of counts at another edge, the signal width
TCR0n operates as an up counter in the capture & one-count mode.
When the channel start trigger (TS0n) is set to 1, TE0n is set to 1 and the TI0k pin start edge detection wait status
When the TI0k start valid edge (rising edge of TI0k when the high-level width is to be measured) is detected, the
As soon as the count value has been captured to the TDR0n register, the OVF bit of the TSR0n register is updated
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF
Whether the high-level width or low-level width of the TI0k pin is to be measured can be selected by using the
Because this function is used to measure the signal width of the TI0k pin input, TS0n cannot be set to 1 while TE0n
CIS0n1, CIS0n0 of TMR0n = 10B: Low-level width is measured.
CIS0n1, CIS0n0 of TMR0n = 11B: High-level width is measured.
Operation clock
Signal width of TI0k input = Period of count clock × ((10000H × TSRn: OVF) + (Capture value of TDR0n + 1))
Remark
Caution The TI0k pin input is sampled using the operating clock selected with the CKS0n bit of the
Figure 6-51. Block Diagram of Operation as Input Signal High-/Low-Level Width Measurement
TI0k pin
TMR0n register, so an error equal to the number of operating clocks occurs.
n = 0 to 7, k = 0 to 6
CK01
CK00
detection
Edge
CHAPTER 6 TIMER ARRAY UNIT
User’s Manual U17854EJ9V0UD
Timer counter
Data register
(TCR0n)
(TDR0n)
controller
Interrupt
Interrupt signal
(INTTM0n)