UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 252

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

250
TMR0n
TOM0
TOE0
TOL0
Remark
TO0
(a) Timer mode register 0n (TMR0n)
(b) Timer output register 0 (TO0)
(c) Timer output enable register 0 (TOE0)
(d) Timer output level register 0 (TOL0)
(e) Timer output mode register 0 (TOM0)
TOM0n
CKS0n
TOE0n
TOL0n
TO0n
Bit n
Bit n
Bit n
Bit n
1/0
15
0
0
0
0
n = 0, 2, 4
Operation clock selection
14
0: Selects CK00 as operation clock of channels n.
1: Selects CK01 as operation clock of channels n.
0
0: Outputs 0 from TO0n.
0: Stops the TO0n output operation by counting operation.
0: Cleared to 0 when TOM0n = 0 (toggle mode).
0: Sets toggle mode.
When One-Shot Pulse Output Function Is Used (Master Channel)
13
0
CCS0n
12
Figure 6-62. Example of Set Contents of Registers
0
Count clock selection
TER0n
MAS
11
0: Selects operation clock.
1
CHAPTER 6 TIMER ARRAY UNIT
Slave/master selection
STS0n2
10
1: Channel 1 is set as master channel.
0
User’s Manual U17854EJ9V0UD
STS0n1
9
0
Start trigger selection
STS0n0
001B: Selects the TI0n pin input valid edge.
8
1
CIS0n1
1/0
7
CIS0n0
1/0
6
Selection of TI0n pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Operation mode of channel n
100B: One-count mode
5
0
4
0
Start trigger during operation
MD0n3
0: Trigger input is invalid.
3
1
MD0n2
2
0
MD0n1
1
0
MD0n0
0
0