UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 255

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Operation
start
During
operation
Operation
stop
TAU stop
Remark
Sets TOE0m (slave) to 1 (only when operation is
resumed).
The TS0n (master) and TS0m (slave) bits of the TS0
register are set to 1 at the same time.
Detects the TI0n pin input valid edge of master channel.
Set values of only the CISn1 and CISn0 bits of the
TMR0n register can be changed.
Set values of the TMR0m, TDR0n, TDR0m registers,
TOM0n, TOM0m, TOL0n, and TOL0m bits cannot be
changed.
The TCR0n and TCR0m registers can always be read.
The TSR0n and TSR0m registers are not used.
Set values of the TO0 and TOE0 registers can be
changed.
The TT0n (master) and TT0m (slave) bits are set to 1 at
the same time.
TOE0m of slave channel is cleared to 0 and value is set
to the TO0m bit.
To hold the TO0m pin output levels
When holding the TO0m pin output levels is not
necessary
The TAU0EN bit of the PER0 register is cleared to 0.
Switches the port mode register to input mode.
The TT0n and TT0m bits automatically return to 0
because they are trigger bits.
n = 0, 2, 4
m = n + 1
The TS0n and TS0m bits automatically return to 0
because they are trigger bits.
Clears TO0m bit to 0 after the value to
be held is set to the port register.
Figure 6-64. Operation Procedure of One-Shot Pulse Output Function (2/2)
Software Operation
CHAPTER 6 TIMER ARRAY UNIT
User’s Manual U17854EJ9V0UD
TE0n and TE0m are set to 1 and the master channel
enters the TI0n input edge detection wait status.
Master channel starts counting.
Master channel loads the value of TDR0n to TCR0n when
the TI0n pin valid input edge is detected, and the counter
starts counting down. When the count value reaches
TCR0n = 0000H, the INTTM0n output is generated, and
the counter stops until the next valid edge is input to the
TI0n pin.
The slave channel, triggered by INTTM0n of the master
channel, loads the value of TDR0m to TCR0m, and the
counter starts counting down. The output level of TO0m
becomes active one count clock after generation of
INTTM0n from the master channel. It becomes inactive
when TCR0m = 0000H, and the counting operation is
stopped.
After that, the above operation is repeated.
TE0n, TE0m = 0, and count operation stops.
The TO0m pin outputs the TO0m set level.
The TO0m pin output levels is held by port function.
The TO0m pin output levels go are into Hi-Z output state.
Power-off status
Counter stops operating.
TCR0n and TCR0m hold count value and stops.
The TO0m output is not initialized but holds current
status.
All circuits are initialized and SFR of each channel is
also initialized.
(The TO0m bit is cleared to 0 and the TO0m pin is set to
port mode.)
Hardware Status
253