UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 256

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.8.3 Operation as multiple PWM output function
the following expressions.
from the TO0p pin. TCR0p loads the value of TDR0p to TCR0p, using INTTM0n of the master channel as a start
trigger, and start counting down. When TCR0p = 0000H, TCR0p outputs INTTM0p and stops counting until the next
start trigger (INTTM0n of the master channel) has been input. The output level of TO0p becomes active one count
clock after generation of INTTM0n from the master channel, and inactive when TCR0p = 0000H.
counts the duty factor, and outputs a PWM waveform from the TO0q pin. TCR0q loads the value of TDR0q to TCR0q,
using INTTM0n of the master channel as a start trigger, and starts counting down. When TCR0q = 0000H, TCR0q
outputs INTTM0q and stops counting until the next start trigger (INTTM0n of the master channel) has been input. The
output level of TO0q becomes active one count clock after generation of INTTM0n from the master channel, and
inactive when TCR0q = 0000H.
same time.
254
By extending the PWM function and using two or more slave channels, many PWM output signals can be produced.
For example, when using two slave channels, the period and duty factor of an output pulse can be calculated by
TCR0n of the master channel operates in the interval timer mode and counts the periods.
TCR0p of the slave channel 1 operates in one-count mode, counts the duty factor, and outputs a PWM waveform
In the same way as TCR0p of the slave channel 1, TCR0q of the slave channel 2 operates in one-count mode,
When channel 0 is used as the master channel as above, up to seven types of PWM signals can be output at the
Caution To rewrite both TDR0n of the master channel and TDR0p of the slave channel 1, write access is
Remark
Remark
Pulse period = {Set value of TDR0n (master) + 1} × Count clock period
Duty factor 1 [%] = {Set value of TDR0m (slave 1)}/{Set value of TDR0n (master) + 1} × 100
Duty factor 2 [%] = {Set value of TDR0m (slave 2)}/{Set value of TDR0n (master) + 1} × 100
necessary at least twice. Since the values of TDR0n and TDR0p are loaded to TCR0n and TCR0p
after INTTM0n is generated from the master channel, if rewriting is performed separately before
and after generation of INTTM0n from the master channel, the TO0p pin cannot output the
expected waveform. To rewrite both TDR0n of the master and TDR0p of the slave, be sure to
rewrite both the registers immediately after INTTM0n is generated from the master channel (This
applies also to TDR0q of the slave channel 2) .
n = 0, 2, 4
n < p < q ≤ 6
Where p and q are consecutive integers following n (p = n + 1, q = n + 2)
Although the duty factor exceeds 100% if the set value of TDR0p (slave 1) > {set value of TDR0n
(master) + 1} or if the {set value of TDR0q (slave 2)} > {set value of TDR0n (master) + 1}, it is
summarized into 100% output.
CHAPTER 6 TIMER ARRAY UNIT
User’s Manual U17854EJ9V0UD