UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 261

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

TAU
default
setting
Channel
default
setting
Remarks 1.
Sets the TAU0EN bit of the PER0 register to 1.
Sets the TPS0 register.
Sets the TMR0n, TMR0p, and TMR0q registers of each
channel to be used (determines operation mode of
channels).
An interval (period) value is set to the TDR0n register of
the master channel, and a duty factor is set to the
TDR0p and TDR0q registers of the slave channel.
Sets slave channel.
Figure 6-69. Operation Procedure When Multiple PWM Output Function Is Used (1/2)
2. p = n + 1; q = n + 2
Determines clock frequencies of CK00 and CK01.
The TOM0p and TOM0q bits of the TOM0 register are
set to 1 (combination operation mode).
Clears the TOL0p and TOL0q bits to 0.
Sets the TO0p and TO0q bits and determines default
level of the TO0p and TO0q outputs.
Sets TOE0p or TOE0q to 1 and enables operation of
TO0p or TO0q.
Clears the port register and port mode register to 0.
n = 0, 2, 4
Software Operation
CHAPTER 6 TIMER ARRAY UNIT
User’s Manual U17854EJ9V0UD
Power-off status
Power-on status. Each channel stops operating.
Channel stops operating.
(Clock is supplied and some power is consumed.)
The TO0p, TO0q pins goes into Hi-Z output state.
The TO0p and TO0q default setting levels are output when
the port mode register is in output mode and the port
register is 0.
TO0p or TO0q does not change because channel stops
operating.
The TO0p and TO0q pins output the TO0p and TO0q set
levels.
(Clock supply is stopped and writing to each register is
disabled.)
(Clock supply is started and writing to each register is
enabled.)
Hardware Status
259