UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 298

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.1 Functions of Clock Output/Buzzer Output Controller
supply to peripheral ICs.
296
The clock output controller is intended for carrier output during remote controlled transmission and clock output for
Buzzer output is a function to output a square wave of buzzer frequency.
One pin can be used to output a clock or buzzer sound.
Two output pins, PCLBUZ0 and PCLBUZ1, are available.
PCLBUZ0 outputs a clock selected by clock output select register 0 (CKS0).
PCLBUZ1 outputs a clock selected by clock output select register 1 (CKS1).
Figure 10-1 shows the block diagram of clock output/buzzer output controller.
Note
Remark f
f
MAIN
f
SUB
PCLOE1
PCLOE0
The PCLBUZ0 and PCLBUZ1 pins can output a clock of up to 10 MHz at 2.7 V ≤ V
exceeding 5 MHz at V
f
MAIN
SUB
: Subsystem clock frequency
: Main system clock frequency
CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
0
0
Prescaler
Figure 9-1. Block Diagram of Clock Output/Buzzer Output Controller
Prescaler
5
8
0
0
3
8
DD
Internal bus
f
f
Internal bus
0
MAIN
MAIN
0
< 2.7 V is prohibited.
f
f
MAIN
/2
/2
MAIN
f
f
SUB
SUB
11
11
CSEL1 CCS12 CCS11 CCS10
CSEL0 CCS02 CCS01 CCS00
to f
to f
to f
Clock output select register 0 (CKS0)
Clock output select register 1 (CKS1)
to f
to f
to f
MAIN
MAIN
MAIN
MAIN
SUB
SUB
User’s Manual U17854EJ9V0UD
/2
/2
/2
/2
/2
/2
13
7
13
4
7
4
Clock/buzzer
Clock/buzzer
controller
controller
PCLOE1
PCLOE0
Output latch
Output latch
(P141)
(P140)
PM141
PM140
PCLBUZ1
PCLBUZ0
DD
Note
Note
. Setting a clock
/INTP7/P141
/INTP6/P140