UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 301

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
<R>
9.4 Operations of Clock Output/Buzzer Output Controller
9.4.1 Operation as output pin
(2) Port mode register 14 (PM14)
One pin can be used to output a clock or buzzer sound.
Two output pins, PCLBUZ0 and PCLBUZ1, are available.
PCLBUZ0 outputs a clock/buzzer selected by clock output select register 0 (CKS0).
PCLBUZ1 outputs a clock/buzzer selected by clock output select register 1 (CKS1).
PCLBUZn is output as the following procedure.
<1> Select the output frequency with bits 0 to 3 (CCSn0 to CCSn2, CSELn) of the clock output select register
<2> Set bit 7 (PCLOEn) of CKSn to 1 to enable clock/buzzer output.
Remarks 1. The controller used for outputting the clock starts or stops outputting the clock one clock after
This register sets port 14 input/output in 1-bit units.
When using the P140/INTP6/PCLBUZ0 and P141/INTP7/PCLBUZ1 pins for clock output/buzzer output, clear
PM140 and PM141 and the output latches of P140 and P141 to 0.
PM14 is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
(CKSn) of the PCLBUZn pin (output in disabled status).
Clock output
2.
PCLOEn
Address: FFF2EH
Symbol
PM14
enabling or disabling clock output (PCLOEn) is switched. At this time, pulses with a narrow width
are not output. Figure 9-4 shows enabling or stopping output using PCLOEn and the timing of
outputting the clock.
n = 0, 1
Narrow pulses are not recognized
PM14n
CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
Figure 9-4. Remote Control Output Application Example
7
0
1
1
1 clock elapsed
Figure 9-3. Format of Port Mode Register 14 (PM14)
After reset: FFH
Output mode (output buffer on)
Input mode (output buffer off)
6
1
User’s Manual U17854EJ9V0UD
5
1
P14n pin I/O mode selection (n = 0, 1)
R/W
4
1
3
1
2
1
PM141
1
PM140
0
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