UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 308

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UPD78F1146AGB-GAH-AX

Manufacturer Part Number
UPD78F1146AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1146AGB-GAH-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1146AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
306
FR2
A/D Converter Mode Register (ADM)
0
0
0
0
1
1
1
Notes 1. This can be set only when 2.7 V ≤ AV
Cautions 1. Set the conversion times with the following conditions.
Remark f
FR1
0
0
1
1
0
0
1
2. This can be set only when 4.0 V ≤ AV
Other than above
2. When rewriting FR2 to FR0, LV1, and LV0 to other than the same data, stop A/D conversion
3. Change LV1 and LV0 from the default value, when 2.3 V ≤ AV
4. The above conversion time does not include clock frequency errors. Select conversion time,
CLK
FR0
0
1
0
1
0
1
1
: CPU/peripheral hardware clock frequency
• 4.0 V ≤ AV
• 2.7 V ≤ AV
• 2.3 V ≤ AV
once (ADCS = 0) beforehand.
taking clock frequency errors into consideration.
LV1
0
0
0
0
0
0
0
LV0
REF
REF
REF
1
1
1
1
1
1
1
≤ 5.5 V: f
< 4.0 V: f
< 2.7 V: f
480/f
320/f
240/f
160/f
120/f
80/f
40/f
Setting prohibited
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CHAPTER 10 A/D CONVERTER
AD
AD
AD
User’s Manual U17854EJ9V0UD
(2) 2.3 V ≤ AV
= 0.6 to 3.6 MHz
= 0.6 to 1.8 MHz
= 0.6 to 1.44 MHz
REF
REF
≤ 5.5 V.
≤ 5.5 V.
Conversion Time Selection
Setting prohibited
60.0
40.0
20.0
REF
f
μ
μ
μ
CLK
s
s
s
≤ 5.5 V
Note 2
= 2 MHz
Setting prohibited
64.0
48.0
32.0
24.0
16.0
Setting prohibited
REF
f
μ
μ
μ
μ
μ
CLK
s
s
s
s
s
Note 1
Note 2
< 2.7 V.
= 5 MHz
f
f
f
f
f
f
f
CLK
CLK
CLK
CLK
CLK
CLK
CLK
Conversion Clock
/12
/8
/6
/4
/3
/2
(f
AD
)

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