UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 341

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(1) Shift register
(2) Lower 8 bits of the serial data register mn (SDRmn)
This is an 8-bit register that converts parallel data into serial data or vice versa.
During reception, it converts data input to the serial pin into parallel data.
When data is transmitted, the value set to this register is output as serial data from the serial output pin.
The shift register cannot be directly manipulated by program.
To read or write the shift register, use the lower 8 bits of serial data register mn (SDRmn).
SDRmn can be read or written in 16-bit units.
The lower 8 bits of SDRmn of SDRmn can be read or written
communication mode.
• CSIp communication … SIOp (CSIp data register)
• UARTq reception … RXDq (UARTq receive data register)
• UARTq transmission … TXDq (UARTq transmit data register)
• IIC10 communication … SIO10 (IIC10 data register)
Reset signal generation clears this register to 0000H.
Remarks 1. After data is received, “0” is stored in bits 0 to 7 in bit portions that exceed the data length.
SDRmn is the transmit/receive data register (16 bits) of channel n. Bits 7 to 0 function as a transmit/receive
buffer register, and bits 15 to 9 are used as a register that sets the division ratio of the operation clock (MCK).
When data is received, parallel data converted by the shift register is stored in the lower 8 bits. When data is
to be transmitted, set transmit to be transferred to the shift register to the lower 8 bits.
The data stored in the lower 8 bits of this register is as follows, depending on the setting of bits 0 to 2
(DLSmn0 to DLSmn2) of the SCRmn register, regardless of the output sequence of the data.
• 5-bit data length (stored in bits 0 to 4 of SDRmn register) (settable in UART mode only)
• 7-bit data length (stored in bits 0 to 6 of SDRmn register)
• 8-bit data length (stored in bits 0 to 7 of SDRmn register)
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 12, 13
p: CSI number (p = 00, 10), q: UART number (q = 0, 1, 3)
CHAPTER 11 SERIAL ARRAY UNIT
User’s Manual U17854EJ9V0UD
Shift register
7
6
Note
as the following SFR, depending on the
Note Writing in 8-bit units is prohibited
5
when the operation is stopped
(SEmn = 0).
4
3
2
1
0
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