UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 344

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

342
Address: F00F0H
(1) Peripheral enable register 0 (PER0)
Symbol
(2) Serial clock select register m (SPSm)
PER0
PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro
that is not used is stopped in order to reduce the power consumption and noise.
When serial array unit 0 is used, be sure to set bit 2 (SAU0EN) of this register to 1.
When serial array unit 1 is used, be sure to set bit 3 (SAU1EN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Cautions 1. When setting serial array unit m, be sure to set SAUmEN to 1 first. If SAUmEN = 0, writing
Remark m: Unit number (m = 0, 1)
SPSm is a 16-bit register that is used to select two types of operation clocks (CKm0, CKm1) that are
commonly supplied to each channel. CKm1 is selected by bits 7 to 4 of SPSm, and CKm0 is selected by bits 3
to 0.
Rewriting SPSm is prohibited when the register is in operation (when SEmn = 1).
SPSm can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of SPSm can be set with an 8-bit memory manipulation instruction with SPSmL.
Reset signal generation clears this register to 0000H.
SAUmEN
RTCEN
2. After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
3. Be sure to clear bits 1 and 6 of PER0 register to 0.
<7>
0
1
After reset: 00H
to a control register of serial array unit m is ignored, and, even if the register is read, only
the default value is read (except for input switch control register (ISC), noise filter enable
register (NFEN0), port input mode register (PIM0), port output mode register (POM0), port
mode registers (PM0, PM1), and port registers (P0, P1)).
clocks have elapsed.
Stops supply of input clock.
• SFR used by serial array unit m cannot be written.
• Serial array unit m is in the reset status.
Supplies input clock.
• SFR used by serial array unit m can be read/written.
Figure 11-4. Format of Peripheral Enable Register 0 (PER0)
6
0
R/W
CHAPTER 11 SERIAL ARRAY UNIT
ADCEN
<5>
User’s Manual U17854EJ9V0UD
Control of serial array unit m input clock
IIC0EN
<4>
SAU1EN
<3>
SAU0EN
<2>
1
0
TAU0EN
<0>