UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 346

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

344
Address: F0110H, F0111H (SMR00) to F0116H, F0117H (SMR03),
SMRmn
(3) Serial mode register mn (SMRmn)
Symbol
SMRmn is a register that sets an operation mode of channel n. It is also used to select an operation clock
(MCK), specify whether the serial clock (SCK) may be input or not, set a start trigger, an operation mode (CSI,
UART, or I
the UART mode.
Rewriting SMRmn is prohibited when the register is in operation (when SEmn = 1). However, the MDmn0 bit
can be rewritten during operation.
SMRmn can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets this register to 0020H.
Caution Be sure to clear bits 13 to 9, 7, 4, and 3 to “0”. Be sure to set bit 5 to “1”.
Remark
F0154H, F0155H (SMR12), F0156H, F0157H (SMR13)
Operation clock MCK is used by the edge detector. In addition, depending on the setting of the CCSmn bit and the
higher 7 bits of the SDRmn register, a transfer clock (TCLK) is generated.
Transfer clock TCLK is used for the shift register, communication controller, output controller, interrupt controller,
and error controller. When CCSmn = 0, the division ratio of MCK is set by the higher 7 bits of the SDRmn register.
Transfer is started when the above source is satisfied after 1 is set to the SSm register.
CKS
CCS
STS
CKS
mn
mn
mn
mn
15
0
1
0
1
0
1
2
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 12, 13
C), and an interrupt source. This register is also used to invert the level of the receive data only in
Operation clock CKm0 set by SPSm register
Operation clock CKm1 set by SPSm register
Divided operation clock MCK specified by CKSmn bit
Clock input from SCK pin (slave transfer in CSI mode)
Only software trigger is valid (selected for CSI, UART transmission, and simplified I
Valid edge of R
CCS
mn
14
Figure 11-6. Format of Serial Mode Register mn (SMRmn) (1/2)
13
0
X
12
D pin (selected for UART reception)
0
CHAPTER 11 SERIAL ARRAY UNIT
11
0
User’s Manual U17854EJ9V0UD
Selection of operation clock (MCK) of channel n
10
Selection of transfer clock (TCLK) of channel n
0
Selection of start trigger source
9
0
STS
mn
8
After reset: 0020H
7
0
mn0
SIS
6
5
1
R/W
4
0
2
3
0
C).
mn2
MD
2
mn1
MD
1
mn0
MD
0