UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 349

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
Address: F0118H, F0119H (SCR00) to F011EH, F011FH (SCR03),
SCRmn
Symbol
Notes 1. When not using CSI01 with EOC01 = 0, error interrupt INTSRE0 may be generated.
Caution Be sure to clear bits 3, 6, and 11 to “0”. Be sure to set bit 2 to “1”.
Remark
F015CH, F015DH (SCR12), F015EH, F015FH (SCR13)
Figure 11-7. Format of Serial Communication Operation Setting Register mn (SCRmn) (2/3)
EOC
Set EOCmn = 0 in the CSI mode, simplified I
Set EOCmn = 1 during UART reception.
Be sure to set PTCmn1, PTCmn0 = 0, 0 in the CSI mode and simplified I
Be sure to clear DIRmn = 0 in the simplified I
When the transfer end interrupt is selected, the interrupt is generated when all stop bits have been completely
transferred.
Set 1 bit (SLCmn1, SLCmn0 = 0, 1) during UART reception and in the simplified I
Set no stop bit (SLCmn1, SLCmn0 = 0, 0) in the CSI mode.
PTC
mn1
SLC
mn1
TXE
DIR
2. 0 is always added regardless of the data contents.
mn
mn
mn
15
0
1
0
1
0
0
1
1
0
0
1
1
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 12, 13
Masks error interrupt INTSREx (INTSRx is not masked).
Enables generation of error interrupt INTSREx (INTSRx is masked if an error occurs).
Inputs/outputs data with MSB first.
Inputs/outputs data with LSB first.
RXE
PTC
mn0
SLC
mn0
mn
14
0
1
0
1
0
1
0
1
Does not output the parity bit.
Outputs 0 parity
Outputs even parity.
Outputs odd parity.
No stop bit
Stop bit length = 1 bit
Stop bit length = 2 bits
Setting prohibited
DAP
mn
13
CKP
mn
12
Selection of masking of error interrupt signal (INTSREx (x = 0, 1, 3))
CHAPTER 11 SERIAL ARRAY UNIT
11
Note 2
Selection of data transfer sequence in CSI and UART modes
0
Transmission
.
User’s Manual U17854EJ9V0UD
EOC
mn
10
PTC
2
2
mn1
C mode, and during UART transmission
C mode.
9
Setting of parity bit in UART mode
Setting of stop bit in UART mode
PTC
mn0
8
After reset: 0087H
DIR
mn
7
Receives without parity
No parity judgment
Judged as even parity.
Judges as odd parity.
6
0
2
C mode.
SLC
mn1
5
R/W
2
SLC
mn0
C mode.
4
Note 1
Reception
..
3
0
DLS
mn2
2
DLS
mn1
1
DLS
mn0
347
0