UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 370

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

368
(1) Register setting
SMR0n
SCR0n
SDR0n
SOE0
SO0
SS0
(a) Serial output register 0 (SO0) … Sets only the bits of the target channel.
(b) Serial output enable register 0 (SOE0) … Sets only the bits of the target channel to 1.
(c) Serial channel start register 0 (SS0) … Sets only the bits of the target channel to 1.
(d) Serial mode register 0n (SMR0n)
(e) Serial communication operation setting register 0n (SCR0n)
(f) Serial data register 0n (SDR0n) (lower 8 bits: SIOp)
Remark
Figure 11-24. Example of Contents of Registers for Master Transmission of 3-Wire Serial I/O
CKS0n
TXE0n
0/1
15
15
15
15
15
15
0
0
0
1
n: Channel number (n = 0, 2), p: CSI number (p = 00, 10)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
CCS0n
RXE0n
14
14
14
14
14
14
0
0
0
0
0
: Setting is fixed in the CSI master transmission mode,
DAP0n
0/1
13
13
13
13
13
13
0
0
0
0
Baud rate setting
CKP0n
0/1
12
12
12
12
12
12
0
0
0
0
11
11
11
11
11
11
0
1
0
0
0
CHAPTER 11 SERIAL ARRAY UNIT
CKO02
EOC0n
0/1
10
10
10
10
10
10
0
0
0
0
User’s Manual U17854EJ9V0UD
PTC0n1
0
9
1
9
9
0
9
0
9
0
9
(CSI00, CSI10)
PTC0n0
CKO00
STS0n
0/1
8
0
0
8
8
0
8
0
8
8
0
DIR0n
Communication starts when these bits are 1 if the data
phase is forward (CKP0n = 0). If the phase is reversed
(CKP0n = 1), communication starts when these bits are 0.
0/1
0
0
7
7
0
7
0
7
7
7
SIS00
0
0
0
6
0
0
6
6
6
6
6
SLC0n1
5
0
0
0
5
1
5
5
5
0
5
: Setting disabled (set to the initial value)
Transmit data setting
SLC0n0
Interrupt sources of channel n
0: Transfer end interrupt
1: Buffer empty interrupt
0
4
0
0
0
4
0
4
4
4
4
SIOp
SS03
0
1
3
3
3
0
3
×
3
0
3
MD0n2
SOE02
DLS0n2
SO02
SS02
0/1
0/1
0/1
0
2
2
2
2
2
2
1
MD0n1
DLS0n1
SS01
1
0
1
1
1
0
1
×
1
1
1
SOE00
MD0n0
DLS0n0
SO00
SS00
0/1
0/1
0/1
0/1
0/1
0
0
0
0
0
0