UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 388

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

386
(2) Operation procedure
Caution
Remark
Even after communication is stopped, the pin level is retained. To resume the operation, re-set the
SO0 register (see Figure 11-43 Procedure for Resuming Master Transmission/Reception).
Figure 11-41. Initial Setting Procedure for Master Transmission/Reception
After setting the PER0 register to 1, be sure to set the SPS0 register after 4 or more clocks
have elapsed.
Changing setting of SOE0 register
Figure 11-42. Procedure for Stopping Master Transmission/Reception
Changing setting of SOE0
Stopping communication
Starting communication
Setting SMR0n register
Setting SCR0n register
Setting SDR0n register
Writing to SS0 register
Starting setting to stop
Setting PER0 register
Setting SPS0 register
Starting initial setting
Setting SO0 register
Setting ST0 register
Setting port
register
CHAPTER 11 SERIAL ARRAY UNIT
User’s Manual U17854EJ9V0UD
Release the serial array unit from the
reset status and start clock supply.
Set the operation clock.
Set an operation mode, etc.
Set a communication format.
Set a transfer baud rate.
Manipulate the SO0n and CKO0n bits
and set an initial output level.
Set the SOE0n bit to 1 and enable data
output of the target channel.
Enable data output and clock output of
the target channel by setting a port
register and a port mode register.
SE0n = 1 when the SS0n bit of the target
channel is set to 1.
Set transmit data to the SIOp register
(bits 7 to 0 of the SDR0n register) and
start communication.
Write 1 to the ST0n bit of the target
channel.
Set the SOE0 register and stop the
output of the target channel.
Stop communication in midway.