UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 406

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
404
(Essential)
(Essential)
(Selective)
(Selective)
(Selective)
(Selective)
(Essential)
(Essential)
(Essential)
Changing setting of SPS0 register
Changing setting of SMR0n register
Manipulating target for communication
Changing setting of SCR0n register
Starting setting for resumption
Starting communication
Figure 11-59. Procedure for Resuming Slave Reception
Writing to SS0 register
Clearing error flag
Port manipulation
Port manipulation
CHAPTER 11 SERIAL ARRAY UNIT
User’s Manual U17854EJ9V0UD
Wait for a clock from the master.
Stop the target for communication or wait
until the target completes its operation.
Disable clock output of the target
channel by setting a port register and a
port mode register.
Change the setting if an incorrect division
ratio of the operation clock is set.
Change the setting if the setting of the
SMR0n register is incorrect.
Change the setting if the setting of the
SCR0n register is incorrect.
Cleared by using SIR0n register if FEF,
PEF, or OVF flag remains set.
Enable clock output of the target channel
by setting a port register and a port mode
register.
SE0n = 1 when the SS0n bit of the target
channel is set to 1.