UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 424

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

422
SMRmn
SCRmn
SDRmn
SOL0
SOL1
(d) Serial output level register m (SOLm) … Sets only the bits of the target channel.
(e) Serial mode register mn (SMRmn)
(f) Serial communication operation setting register mn (SCRmn)
(g) Serial data register mn (SDRmn) (lower 8 bits: TXDq)
Remark
CKSmn
TXEmn
0/1
15
15
15
15
15
0
0
1
Figure 11-71. Example of Contents of Registers for UART Transmission of UART
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), mn = 00, 02, 12,
q: UART number (q = 0, 1, 3)
0/1: Set to 0 or 1 depending on the usage of the user
CCSmn
RXEmn
14
14
14
14
14
0
0
0
0
: Setting is fixed in the UART transmission mode,
DAPmn
13
13
13
13
13
0
0
0
0
Baud rate setting
Setting of parity bit
00B: No parity
01B: 0 parity
10B: Even parity
11B: Odd parity
CKPmn
12
12
12
12
12
0
0
0
0
11
11
11
11
11
0
0
0
0
CHAPTER 11 SERIAL ARRAY UNIT
EOCmn
(UART0, UART1, UART3) (2/2)
10
10
10
10
10
0
0
0
0
User’s Manual U17854EJ9V0UD
PTCmn1
0/1
9
0
9
9
0
9
0
9
PTCmn0
STSmn
0/1
8
0
8
8
0
8
0
8
0
0: Forward (normal) transmission
0: Forward (normal) transmission
DIRmn
0/1
0
7
7
0
7
0
7
7
SISmn0
1: Reverse transmission
1: Reverse transmission
0
0
0
0
6
6
6
6
6
: Setting disabled (set to the initial value)
SLCmn1
0/1
0
0
5
1
5
5
5
5
Transmit data setting
SLCmn0
0/1
0
0
4
0
4
4
4
4
Interrupt sources of channel n
0: Transfer end interrupt
1: Buffer empty interrupt
TXDq
Setting of stop bit
01B: Appending 1 bit
10B: Appending 2 bits
3
0
3
0
3
0
3
0
3
DLSmn2
MDmn2
SOL02
SOL12
0/1
0/1
0
2
1
2
2
2
2
MDmn1
DLSmn1
0/1
1
1
0
1
0
1
1
1
MDmn0
DLSmn0
SOL00
0/1
0/1
0/1
0
0
0
0
0
0