UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 478

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.2 Configuration of Serial Interface IIC0
476
Serial interface IIC0 includes the following hardware.
(1) IIC shift register 0 (IIC0)
(2) Slave address register 0 (SVA0)
IIC0 is used to convert 8-bit serial data to 8-bit parallel data and vice versa in synchronization with the serial
clock. IIC0 can be used for both transmission and reception.
The actual transmit and receive operations can be controlled by writing and reading operations to IIC0.
Cancel the wait state and start data transfer by writing data to IIC0 during the wait period.
IIC0 can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears IIC0 to 00H.
Cautions 1. Do not write data to IIC0 during data transfer.
This register stores local addresses when in slave mode.
SVA0 can be set by an 8-bit memory manipulation instruction.
However, rewriting to this register is prohibited while STD0 = 1 (while the start condition is detected).
Reset signal generation clears SVA0 to 00H.
Note Bit 0 is fixed to 0.
Address: FFF50H
Address: FFF53H
Symbol
Symbol
SVA0
IIC0
2. Write or read IIC0 only during the wait period. Accessing IIC0 in a communication state
Registers
Control registers
other than during the wait period is prohibited. When the device serves as the master,
however, IIC0 can be written only once after the communication trigger bit (STT0) is set to
1.
Item
Figure 12-4. Format of Slave Address Register 0 (SVA0)
7
7
Table 12-1. Configuration of Serial Interface IIC0
Figure 12-3. Format of IIC Shift Register 0 (IIC0)
After reset: 00H
After reset: 00H
CHAPTER 12 SERIAL INTERFACE IIC0
6
6
IIC shift register 0 (IIC0)
Slave address register 0 (SVA0)
Peripheral enable register 0 (PER0)
IIC control register 0 (IICC0)
IIC status register 0 (IICS0)
IIC flag register 0 (IICF0)
IIC clock select register 0 (IICCL0)
IIC function expansion register 0 (IICX0)
Port mode register 6 (PM6)
Port register 6 (P6)
User’s Manual U17854EJ9V0UD
5
5
R/W
R/W
4
4
Configuration
3
3
2
2
1
1
0
Note
0
0