UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 486

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

484
(3) IIC status register 0 (IICS0)
Address: FFF56H
Symbol
This register indicates the status of I
IICS0 is read by a 1-bit or 8-bit memory manipulation instruction only when STT0 = 1 and during the wait
period.
Reset signal generation clears this register to 00H.
IICS0
Note This register is also cleared when a 1-bit memory manipulation instruction is executed for bits
Remark
Condition for clearing (MSTS0 = 0)
• When a stop condition is detected
• When ALD0 = 1 (arbitration loss)
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
Condition for clearing (ALD0 = 0)
• Automatically cleared after IICS0 is read
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
Condition for clearing (EXC0 = 0)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
MSTS0
MSTS0
EXC0
ALD0
<7>
0
1
0
1
0
1
other than IICS0. Therefore, when using the ALD0 bit, read the data of this bit before the data
of the other bits.
LREL0:
IICE0:
After reset: 00H
Extension code was not received.
Extension code was received.
Slave device status or communication standby status
Master device communication status
This status means either that there was no arbitration or that the arbitration result was a “win”.
This status indicates the arbitration result was a “loss”. MSTS0 is cleared.
Figure 12-7. Format of IIC Status Register 0 (IICS0) (1/3)
ALD0
<6>
Bit 6 of IIC control register 0 (IICC0)
Bit 7 of IIC control register 0 (IICC0)
CHAPTER 12 SERIAL INTERFACE IIC0
EXC0
<5>
2
C.
User’s Manual U17854EJ9V0UD
R
COI0
<4>
Note
Detection of extension code reception
Detection of arbitration loss
TRC0
Master device status
<3>
Condition for setting (MSTS0 = 1)
• When a start condition is generated
Condition for setting (ALD0 = 1)
• When the arbitration result is a “loss”.
Condition for setting (EXC0 = 1)
• When the higher four bits of the received address
data is either “0000” or “1111” (set at the rising edge
of the eighth clock).
ACKD0
<2>
STD0
<1>
SPD0
<0>