UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 496

no-image

UPD78F1146AGB-GAH-AX

Manufacturer Part Number
UPD78F1146AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1146AGB-GAH-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1146AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
12.5.4 Transfer clock setting method
494
(1) Selection clock setting method on the master side
(2) Selection clock setting method on the slave side
The selection clock is set using a combination of bits 3, 1, and 0 (SMC0, CL01, and CL00) of IIC clock select
register 0 (IICCL0) and bit 0 (CLX0) of IIC function expansion register 0 (IICX0).
The I
For example, the I
is calculated using following expression.
To use as slave, set the bits 3, 1, and 0 (SMC0, CL01, CL00) of the IIC clock selection register (IICL0) and the
bit 0 (CLX0) of the IIC function expansion register 0 (IICX0) according to the f
Range) and IIC Operation Mode (Normal or Fast ) as defined in Table 12-3. Selection Clock Setting.
2
f
f
C transfer clock frequency (f
SCL
SCL
m = 24, 44, 48, 88, 96, 172, 344 (see Table 12-3 Selection Clock Setting)
T: 1/f
t
t
= 1/(m × T + t
R
F
= 1/(88 × 238.7 ns + 200 ns + 50 ns) ≅ 47.0 kHz
: SCL0 fall time
: SCL0 rise time
SCL0
CLK
SCL0
2
C transfer clock frequency (f
inversion
R
+ t
t
R
F
)
CHAPTER 12 SERIAL INTERFACE IIC0
SCL
) is calculated using the following expression.
m/2 × T
User’s Manual U17854EJ9V0UD
m × T + t
SCL0
SCL
) when f
inversion
R
+ t
F
t
F
CLK
= 4.19 MHz, m = 88, t
m/2 × T
SCL0
inversion
CLK
(Selectable Selection Clock
R
= 200 ns, and t
F
= 50 ns

Related parts for UPD78F1146AGB-GAH-AX