UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 507

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.5.15 Communication reservation
(1) When communication reservation function is enabled (bit 0 (IICRSV) of IIC flag register 0 (IICF0) = 0)
To start master device communications when not currently using a bus, a communication reservation can be
made to enable transmission of a start condition when the bus is released. There are two modes under which
the bus is not used.
• When arbitration results in neither master nor slave operation
• When an extension code is received and slave operation is disabled (ACK is not returned and the bus was
If bit 1 (STT0) of IICC0 is set to 1 while the bus is not used (after a stop condition is detected), a start condition
is automatically generated and wait state is set.
If an address is written to IIC shift register 0 (IIC0) after bit 4 (SPIE0) of IICC0 was set to 1, and it was detected
by generation of an interrupt request signal (INTIIC0) that the bus was released (detection of the stop
condition), then the device automatically starts communication as the master. Data written to IIC0 before the
stop condition is detected is invalid.
When STT0 has been set to 1, the operation mode (as start condition or as communication reservation) is
determined according to the bus status.
• If the bus has been released .........................................a start condition is generated
• If the bus has not been released (standby mode) .........communication reservation
Check whether the communication reservation operates or not by using MSTS0 (bit 7 of IIC status register 0
(IICS0)) after STT0 is set to 1 and the wait time elapses.
The wait periods, which should be set via software, are listed in Table 12-6.
Figure 12-21 shows the communication reservation timing.
released by setting bit 6 (LREL0) of IIC control register 0 (IICC0) to 1 and saving communication).
CLX0
0
0
0
0
0
0
0
0
1
1
1
1
SMC0
0
0
0
0
1
1
1
1
1
1
1
1
CHAPTER 12 SERIAL INTERFACE IIC0
CL01
0
0
1
1
0
0
1
1
0
0
1
1
Table 12-7. Wait Periods
User’s Manual U17854EJ9V0UD
CL00
0
1
0
1
0
1
0
1
0
1
0
1
101 clocks
43 clocks
85 clocks
23 clocks
27 clocks
51 clocks
15 clocks
27 clocks
9 clocks
Wait Period
505