UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 511

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.5.16 Cautions
(1) When STCEN (bit 1 of IIC flag register 0 (IICF0)) = 0
(2) When STCEN = 1
(3) If other I
(4) Determine the transfer clock frequency by using SMC0, CL01, CL00 (bits 3, 1, and 0 of IICL0), and CLX0 (bit 0
(5) Setting STT0 and SPT0 (bits 1 and 0 of IICC0) again after they are set and before they are cleared to 0 is
(6) When transmission is reserved, set SPIE0 (bit 4 of IICL0) to 1 so that an interrupt request is generated when
Immediately after I
1) is recognized regardless of the actual bus status. When changing from a mode in which no stop condition
has been detected to a master device communication mode, first generate a stop condition to release the bus,
then perform master device communication.
When using multiple masters, it is not possible to perform master device communication when the bus has not
been released (when a stop condition has not been detected).
Use the following sequence for generating a stop condition.
<1> Set IIC clock select register 0 (IICCL0).
<2> Set bit 7 (IICE0) of IIC control register 0 (IICC0) to 1.
<3> Set bit 0 (SPT0) of IICC0 to 1.
Immediately after I
regardless of the actual bus status. To generate the first start condition (STT0 (bit 1 of IIC control register 0
(IICC0)) = 1), it is necessary to confirm that the bus has been released, so as to not disturb other
communications.
If I
pin is low and the SCL0 pin is high, the macro of I
start condition). If the value on the bus at this time can be recognized as an extension code, ACK is returned,
but this interferes with other I
<1> Clear bit 4 (SPIE0) of IICC0 to 0 to disable generation of an interrupt request signal (INTIIC0) when the
<2> Set bit 7 (IICE0) of IICC0 to 1 to enable the operation of I
<3> Wait for detection of the start condition.
<4> Set bit 6 (LREL0) of IICC0 to 1 before ACK is returned (4 to 80 clocks after setting IICE0 to 1), to forcibly
of IICX0) before enabling the operation (IICE0 = 1). To change the transfer clock frequency, clear IICE0 to 0
once.
prohibited.
the stop condition is detected. Transfer is started when communication data is written to IIC0 after the interrupt
request is generated. Unless the interrupt is generated when the stop condition is detected, the device stops
in the wait state because the interrupt request is not generated when communication is started. However, it is
not necessary to set SPIE0 to 1 when MSTS0 (bit 7 of IICS0) is detected by software.
2
C operation is enabled and the device participates in communication already in progress when the SDA0
stop condition is detected.
disable detection.
2
C communications are already in progress
2
C operation is enabled (IICE0 = 1), the bus communication status (IICBSY (bit 6 of IICF0) =
2
C operation is enabled (IICE0 = 1), the bus released status (IICBSY = 0) is recognized
2
C communications. To avoid this, start I
CHAPTER 12 SERIAL INTERFACE IIC0
User’s Manual U17854EJ9V0UD
2
C recognizes that the SDA0 pin has gone low (detects a
2
C.
2
C in the following sequence.
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