UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 558

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UPD78F1146AGB-GAH-AX

Manufacturer Part Number
UPD78F1146AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1146AGB-GAH-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1146AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
556
Address: FFFBCH (DRC0), FFFBDH (DRC1)
Symbol
DRCn
(2) DMA operation control register n (DRCn)
DRCn is a register that is used to enable or disable transfer of DMA channel n.
Rewriting bit 7 (DENn) of this register is prohibited during operation (when DSTn = 1).
DRCn can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Caution The DSTn flag is automatically cleared to 0 when a DMA transfer is completed.
Remark
DMAC waits for a DMA trigger when DSTn = 1 after DMA operation is enabled (DENn = 1).
DMAC waits for a DMA trigger when DSTn = 1 after DMA operation is enabled (DENn = 1).
When a software trigger (STGn) or the start source trigger set by IFCn3 to IFCn0 is input, DMA transfer is started.
When DMA transfer is completed after that, this bit is automatically cleared to 0.
Write 0 to this bit to forcibly terminate DMA transfer under execution.
DENn
DSTn
DENn
<7>
0
1
0
1
Writing the DENn flag is enabled only when DSTn = 0. When a DMA transfer is terminated
without waiting for generation of the interrupt (INTDMAn) of DMAn, therefore, set DSTn to 0
and then DENn to 0 (for details, refer to 14.5.7 Forcible termination by software).
n: DMA channel number (n = 0, 1)
Figure 14-5. Format of DMA Operation Control Register n (DRCn)
Disables operation of DMA channel n (stops operating cock of DMA).
Enables operation of DMA channel n.
DMA transfer of DMA channel n is completed.
DMA transfer of DMA channel n is not completed (still under execution).
6
0
CHAPTER 14 DMA CONTROLLER
After reset: 00H
5
0
User’s Manual U17854EJ9V0UD
4
0
DMA operation enable flag
R/W
DMA transfer mode flag
3
0
0
2
1
0
DSTn
<0>

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