UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 596

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.4.3 Multiple interrupt servicing
(IE = 1). When an interrupt request is acknowledged, interrupt request acknowledgment becomes disabled (IE = 0).
Therefore, to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during
interrupt servicing to enable interrupt acknowledgment.
interrupt priority control. Two types of priority control are available: default priority control and programmable priority
control. Programmable priority control is used for multiple interrupt servicing.
currently being serviced is generated, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority
lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged
for multiple interrupt servicing. Interrupt requests that are not enabled because interrupts are in the interrupt disabled
state or because they have a lower priority are held pending. When servicing of the current interrupt ends, the
pending interrupt request is acknowledged following execution of at least one main processing instruction execution.
shows multiple interrupt servicing examples.
594
Interrupt Being Serviced
Maskable interrupt
Software interrupt
Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt.
Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected
Moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to
In the interrupt enabled state, if an interrupt request with a priority equal to or higher than that of the interrupt
Table 15-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and Figure 15-10
Remarks 1.
Multiple Interrupt Request
Table 15-5. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing
2. ×: Multiple interrupt servicing disabled
3. ISP0, ISP1, and IE are flags contained in the PSW.
4. PR is a flag contained in PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L,
ISP1 = 0, ISP0 = 0: An interrupt of level 1 or level 0 is being serviced.
ISP1 = 0, ISP0 = 1: An interrupt of level 2 is being serviced.
ISP1 = 1, ISP0 = 0: An interrupt of level 3 is being serviced.
ISP1 = 1, ISP0 = 1: Wait for An interrupt acknowledgment.
IE = 0: Interrupt request acknowledgment is disabled.
IE = 1: Interrupt request acknowledgment is enabled.
PR11H, PR12L, and PR12H.
PR = 00: Specify level 0 with ××PR1× = 0, ××PR0× = 0 (higher priority level)
PR = 01: Specify level 1 with ××PR1× = 0, ××PR0× = 1
PR = 10: Specify level 2 with ××PR1× = 1, ××PR0× = 0
PR = 11: Specify level 3 with ××PR1× = 1, ××PR0× = 1 (lower priority level)
: Multiple interrupt servicing enabled
ISP1 = 0
ISP0 = 0
ISP1 = 0
ISP0 = 1
ISP1 = 1
ISP0 = 0
ISP1 = 1
ISP0 = 1
IE = 1
Priority Level 0
(PR = 00)
CHAPTER 15 INTERRUPT FUNCTIONS
IE = 0
×
×
×
×
×
During Interrupt Servicing
User’s Manual U17854EJ9V0UD
IE = 1
Priority Level 1
×
(PR = 01)
Maskable Interrupt Request
IE = 0
×
×
×
×
×
IE = 1
Priority Level 2
×
×
(PR = 10)
IE = 0
×
×
×
×
×
IE = 1
Priority Level 3
×
×
×
(PR = 11)
IE = 0
×
×
×
×
×
Software
Interrupt
Request